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*.vmfset: update rules to cover 2017.4-2018.2

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wfjm
2018-08-24 20:52:21 +02:00
parent 1e31571849
commit ac16d6d27e
15 changed files with 284 additions and 47 deletions
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3
doc/CHANGELOG.md
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@@ -20,6 +20,9 @@ The full set of tests is only run for tagged releases.
### Summary
- xviv_msg_filter: allow {yyyy.x} tags (in addition to ranges)
- xviv_msg_summary: check also for .bit and .dcp files
- get vivado 2017.2 ready; all designs build under 2017.2 and 2018.2
- *.vmfset: update rules to cover 2017.4-2018.2
<!-- --------------------------------------------------------------------- -->
---

8
rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset
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@@ -1,7 +1,13 @@
# $Id: sys_tst_rlink_arty.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_rlink_arty.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05

8
rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset
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@@ -1,7 +1,13 @@
# $Id: sys_tst_rlink_b3.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_rlink_b3.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05

8
rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset
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@@ -1,7 +1,13 @@
# $Id: sys_tst_rlink_c7.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_rlink_c7.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
# --> rlink_sp1c doesn't use CE_USEC # OK 2017-06-05

8
rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset
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@@ -1,7 +1,13 @@
# $Id: sys_tst_rlink_n4.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_rlink_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
# --> I_BTNRST_N unused in design # OK 2016-06-05

10
rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset
View File

@@ -1,8 +1,14 @@
# $Id: sys_tst_serloop1_n4.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_serloop1_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# +++# port driven by constant --------------------------------------
# --> RGBLED0 unused # OK 2016-06-05
i [Synth 8-3917] O_RGBLED0[\d]
@@ -32,7 +38,7 @@ I [Synth 8-6014] _reg # generic
i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*]
# ++==+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
# +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps
I [Physopt 32-742] # BRAM Flop Optimization

8
rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset
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@@ -1,7 +1,13 @@
# $Id: sys_tst_serloop2_n4.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_serloop2_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic

8
rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset
View File

@@ -1,7 +1,13 @@
# $Id: sys_tst_snhumanio_b3.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_snhumanio_b3.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic

8
rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset
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@@ -1,7 +1,13 @@
# $Id: sys_tst_snhumanio_n4.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_snhumanio_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic

24
rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset
View File

@@ -1,7 +1,13 @@
# $Id: sys_tst_sram_c7.vmfset 912 2017-06-11 18:30:03Z mueller $
# $Id: sys_tst_sram_c7.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
@@ -27,6 +33,7 @@ i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC)
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{:2017.4}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2017-06-11
i [Synth 8-3332] HIO/R_REGS_reg[led][\d*]
@@ -42,6 +49,21 @@ i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[usec]
# --> CES_USEC isn't used # OK 2017-06-11
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
{2018.1:}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[led][\d*].* sn_humanio_emu_rbus
i [Synth 8-3332] R_REGS_reg[dsp_dp][\d*].* sn_humanio_emu_rbus
i [Synth 8-3332] R_REGS_reg[dsp_dat][\d*].* sn_humanio_emu_rbus
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> only RB_STAT 0,1 used by tst_sram # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_BREGS_reg[stat][(2|3)]
# --> CE_USEC isn't used (also not in rlink_sp2c) # OK 2018-08-12
# --> CES_USEC isn't used # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps

20
rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset
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@@ -1,7 +1,13 @@
# $Id: sys_tst_sram_n4.vmfset 908 2017-06-05 21:03:06Z mueller $
# $Id: sys_tst_sram_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
@@ -32,6 +38,8 @@ I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
i [Synth 8-3332] HIO/IOB_LED/R_DO_reg[\d*]
i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*]
{:2017.4}
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
@@ -42,6 +50,16 @@ i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[usec]
# --> CES_USEC isn't used # OK 2016-06-05
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
{2018.1:}
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> only RB_STAT 0,1 used by tst_sram # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_BREGS_reg[stat][(2|3)]
# --> CE_USEC isn't used (also not in rlink_sp2c) # OK 2018-08-12
# --> CES_USEC isn't used # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* module clkdivce
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps

99
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
View File

@@ -1,7 +1,16 @@
# $Id: sys_w11a_br_arty.vmfset 909 2017-06-09 16:21:55Z mueller $
# $Id: sys_w11a_br_arty.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# binding instance .. which has no pins ------------------------
I [Synth 8-115] # generic
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
@@ -49,40 +58,104 @@ i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> dmcmon not configured, snum not used # OK 2017-06-06
i [Synth 8-3332] SEQ/SNUM0.R_VMWAIT_reg
{2017.1:}
{2017.1:2017.4}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2017-06-06
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] HIO/IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2017-06-06
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> mawidth=4, nblock=11, so some cellen unused # OK 2017-06-06
# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05
i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d]
# --> indeed no types with [3] set # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
{2017.1:2017.3}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> [8] is for DZ11TX, not yet available # OK 2017-06-06
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2017-06-06
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> monitor outputs moneop,monattn currently not used # OK 2017-06-06
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> dmcmon not configured, snum not used
# --> dmcmon not configured, snum not used # OK 2017-06-06
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2017-06-06
{2017.4}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
# --> not yet used # OK 2018-08-11
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_core
# --> [8] is for DZ11TX, not yet available # OK 2018-08-11
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_core
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-08-11
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_core
# --> dmcmon not configured, snum not used # OK 2018-08-11
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_core # OK 2018-08-11
{2018.1:}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2017-06-06
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[usec]
# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[cellen][1\d]
# --> indeed no types with [3] set # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-11
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
# --> not yet used # OK 2018-08-11
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> [8] is for DZ11TX, not yet available # OK 2017-06-06
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-08-11
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> dmcmon not configured, snum not used
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2018-08-11
{:}
# INFO: encoded FSM with state register as --------------------
# test for sys_w11a_br_arty that all FSMs are one_hot
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox'
r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core'
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps

41
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
View File

@@ -1,7 +1,16 @@
# $Id: sys_w11a_b3.vmfset 909 2017-06-09 16:21:55Z mueller $
# $Id: sys_w11a_b3.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# binding instance .. which has no pins ------------------------
I [Synth 8-115] # generic
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
@@ -49,10 +58,6 @@ I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> usec not used for serport clock domain # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05
@@ -73,8 +78,34 @@ i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c
# --> dmcmon not configured, snum not used # OK 2017-06-06
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer
{2017.1:2017.4}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox
{2018.1:}
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-12
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
{:}
# INFO: encoded FSM with state register as --------------------
# test for sys_w11a_b3 that all FSMs are one_hot
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox'
r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core'
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps

44
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
View File

@@ -1,7 +1,16 @@
# $Id: sys_w11a_c7.vmfset 916 2017-06-25 13:30:07Z mueller $
# $Id: sys_w11a_c7.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# binding instance .. which has no pins ------------------------
I [Synth 8-115] # generic
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567]
@@ -53,14 +62,8 @@ i [Synth 8-3332] R_REGS_reg[dsp_dp][(4|5|6|7)]
{2017.1:}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> usec not used for serport clock domain # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-24
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> not yet used # OK 2017-06-24
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> mawidth=4, nblock=11, so some cellen unused # OK 2017-06-25
i [Synth 8-3332] R_REGS_reg[cellen][1\d].* pdp11_bram_memctl
# --> indeed no types with [3] set # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2017-06-24
@@ -71,18 +74,37 @@ i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2017-06-24
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> monitor outputs moneop,monattn currently not used # OK 2017-06-24
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop].* rlink_sp2c
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
# --> upper 4 DSP_DP unused # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[dsp_dp][(4|5|6|7)]
{2017.1:2017.4}
# --> usec not used for serport clock domain # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# --> monitor outputs moneop,monattn currently not used # OK 2017-06-24
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop].* rlink_sp2c
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-24
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> mawidth=4, nblock=11, so some cellen unused # OK 2017-06-25
i [Synth 8-3332] R_REGS_reg[cellen][1\d].* pdp11_bram_memctl
{2018.1:}
# --> usec not used for serport clock domain # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* sys_w11a_c7
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] R_LREGS_reg[moneop].* rlink_core
i [Synth 8-3332] R_LREGS_reg[monattn].* rlink_core
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-12
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[cellen][1\d].* sys_w11a_c7
{:}
# INFO: encoded FSM with state register as --------------------
# test for sys_w11a_n4 that all FSMs are one_hot
# test for sys_w11a_c7 that all FSMs are one_hot
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud'

34
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
View File

@@ -1,7 +1,16 @@
# $Id: sys_w11a_n4.vmfset 909 2017-06-09 16:21:55Z mueller $
# $Id: sys_w11a_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# binding instance .. which has no pins ------------------------
I [Synth 8-115] # generic
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567]
@@ -51,10 +60,6 @@ I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> only 4 MB out of 16 MB used # OK 2017-06-06
i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[20]
i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[21]
# --> usec not used for serport clock domain # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> indeed no types with [3] set # OK 2017-06-06
@@ -67,11 +72,26 @@ i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2017-06-06
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
{2017.1:2017.4}
# --> usec not used for serport clock domain # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> monitor outputs moneop,monattn currently not used # OK 2017-06-06
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop].* rlink_sp2c
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
{2018.1:}
# --> usec not used for serport clock domain # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* sys_w11a_n4
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-12
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] R_LREGS_reg[moneop].* rlink_core
i [Synth 8-3332] R_LREGS_reg[monattn].* rlink_core
{:}