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KW11-P ext evt selectable; pc11copy with kw11 stress

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- ibd_kw11p:
  - add csr.ir (rem; as intreq monitor)
  - the source of external events (rate=11) is now selectable vai an new rem
    accessible csr.erate field. options: sysclk, 1 Mhz, extevt, none
- w11a_hbpt/test_hbpt_basics.tcl: leave system in clean state at end
- mcode/pc11/pc11copy.mac: add kw11-l/p stress (further ECO-030 testing)
This commit is contained in:
wfjm
2019-04-26 10:44:42 +02:00
parent bc150d2f57
commit b08d8162dc
7 changed files with 283 additions and 134 deletions
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60
rtl/ibus/ibd_kw11p.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibd_kw11p.vhd 1056 2018-10-13 16:01:17Z mueller $
-- $Id: ibd_kw11p.vhd 1138 2019-04-26 08:14:56Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -26,6 +26,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-24 1138 1.1 add csr.ir; add rem controllable options for
-- RATE=11: sysclk, 1 Mhz, extevt, none
-- 2018-09-09 1043 1.0 Initial version
------------------------------------------------------------------------------
@@ -63,6 +65,8 @@ architecture syn of ibd_kw11p is
constant ibaddr_ctr : slv2 := "10"; -- ctr address offset
constant csr_ibf_err : integer := 15;
constant csr_ibf_ir : integer := 10;
subtype csr_ibf_erate is integer range 9 downto 8;
constant csr_ibf_done : integer := 7;
constant csr_ibf_ie : integer := 6;
constant csr_ibf_fix : integer := 5;
@@ -75,6 +79,11 @@ architecture syn of ibd_kw11p is
constant rate_10k : slv2 := "01";
constant rate_line : slv2 := "10";
constant rate_ext : slv2 := "11";
constant erate_sclk : slv2 := "00";
constant erate_usec : slv2 := "01";
constant erate_ext : slv2 := "10";
constant erate_noop : slv2 := "11";
constant dwidth : natural := 4; -- decade divider
constant ddivide : natural := 10;
@@ -85,6 +94,7 @@ architecture syn of ibd_kw11p is
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
erate : slv2; -- ext rate mode
err : slbit; -- re-interrupt error
done : slbit; -- counter wrap occured
ie : slbit; -- interrupt enable
@@ -108,6 +118,7 @@ architecture syn of ibd_kw11p is
constant regs_init : regs_type := (
'0', -- ibsel
"00", -- erate
'0','0','0','0','0', -- err,done,ie,updn,mode
"00",'0', -- rate,run
(others=>'0'), -- csb
@@ -131,6 +142,7 @@ begin
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.erate <= N_REGS.erate; -- keep ERATE field
R_REGS.lcnt <= N_REGS.lcnt; -- don't clear clock dividers
R_REGS.d1cnt <= N_REGS.d1cnt; -- "
R_REGS.d2cnt <= N_REGS.d2cnt; -- "
@@ -162,7 +174,14 @@ begin
ievt := '0';
n.evtext := EXTEVT; -- buffer
n.evtext := '0';
case r.erate is
when erate_sclk => n.evtext := '1';
when erate_usec => n.evtext := CE_USEC;
when erate_ext => n.evtext := EXTEVT;
when erate_noop => n.evtext := '0';
when others => null;
end case;
n.evt100k := '0'; -- one shot
n.evt10k := '0'; -- one shot
n.evtline := '0'; -- one shot
@@ -193,23 +212,34 @@ begin
n.done := '0'; -- done is read and clear
end if;
if ibwr = '1' then
n.evtfix := IB_MREQ.din(csr_ibf_fix);
n.ie := IB_MREQ.din(csr_ibf_ie);
n.updn := IB_MREQ.din(csr_ibf_updn);
n.mode := IB_MREQ.din(csr_ibf_mode);
n.rate := IB_MREQ.din(csr_ibf_rate);
n.run := IB_MREQ.din(csr_ibf_run);
if IB_MREQ.din(csr_ibf_ie)='0' then
n.intreq := '0';
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibwr = '1' then
n.evtfix := IB_MREQ.din(csr_ibf_fix);
n.ie := IB_MREQ.din(csr_ibf_ie);
n.updn := IB_MREQ.din(csr_ibf_updn);
n.mode := IB_MREQ.din(csr_ibf_mode);
n.rate := IB_MREQ.din(csr_ibf_rate);
n.run := IB_MREQ.din(csr_ibf_run);
if IB_MREQ.din(csr_ibf_ie)='0' then
n.intreq := '0';
end if;
end if;
else -- rri ---------------------
idout(csr_ibf_ir) := r.intreq;
idout(csr_ibf_erate) := r.erate;
if ibwr = '1' then
n.erate := IB_MREQ.din(csr_ibf_erate);
end if;
end if;
when ibaddr_csb => -- CSB -- count set buffer -----------
idout := (others=>'0'); -- csb is not readable, return zero !
if ibwr = '1' then
n.csb := IB_MREQ.din;
n.evtload := '1';
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibwr = '1' then
n.csb := IB_MREQ.din;
n.evtload := '1';
end if;
end if;
when ibaddr_ctr => -- CTR -- counter --------------------

85
tools/mcode/pc11/pc11copy.mac
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@@ -1,9 +1,10 @@
; $Id: pc11copy.mac 1136 2019-04-24 09:27:28Z mueller $
; $Id: pc11copy.mac 1138 2019-04-26 08:14:56Z mueller $
; Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
; License disclaimer see License.txt in $RETROBASE directory
;
; Revision History:
; Date Rev Version Comment
; 2019-04-25 1138 1.1 add kw11-l/p stress
; 2019-04-21 1134 1.0 Initial version
;
; copy input to output tape
@@ -11,21 +12,35 @@
; definitions ----------------------------------------------
;
.include |lib/defs_cpu.mac|
.include |lib/defs_kwl.mac|
.include |lib/defs_kwp.mac|
.include |lib/defs_pc.mac|
bsize = 256.
bsize = 256. ; elasticity ring buffer size
kpwait = 997. ; kp wait (in cycles, intentionally prime)
cbsize = 250. ; kp-per-kl trace buffer size (for last 5 sec)
;
; vector area ----------------------------------------------
;
.include |lib/vec_cpucatch.mac|
.include |lib/vec_devcatch.mac|
. = v..ptr
. = v..ptr ; PC11 pr vector
.word vh.ptr
.word cp.pr7
. = v..ptp
. = v..ptp ; PC11 pp vector
.word vh.ptp
.word cp.pr7
. = v..kwl ; KW11-L vector
.word vh.kwl
.word cp.ars!cp.pr7 ; use alt-reg-set !
. = v..kwp ; KW11-P vector
.word vh.kwp
.word cp.ars!cp.pr7 ; use alt-reg-set !
;
; stack area -----------------------------------------------
;
@@ -34,7 +49,7 @@ stack:
;
; code area ------------------------------------------------
;
; all context is in 6 register
; all context of the pr-to-pp copy is in 6 registers
; r0 bytes read ; !! visible in wait !!
; r1 bytes written
; r2 bytes in buffer
@@ -63,6 +78,14 @@ start1: mov #stack,sp ; setup stack
clr r0 ; clear rcnt
clr r1 ; clear wcnt
;
clr klcnt
clr kpcnt
mov #cbuf,cbptr
;
spl 7
mov #kl.ie,@#kl.csr ; start kw11-l
mov #kpwait,@#kp.csb ; load kw11-p counter
mov #<kp.ie!kp.rep!kp.rex!kp.run>,@#kp.csr ; kw11-p: ext down repeat
mov #<pr.ie!pr.ena>,@#pr.csr ; start reader
spl 0 ; allow interrupts
3$: wait ; and idle
@@ -130,10 +153,62 @@ vh.ptp: tst @#pp.csr ; punch error
perr: halt ; puncher error halt
br perr
;
; kw11-l interrupt handler ------------------------
; checks that
; 1. kl.mon is set (to detect spurious interrupts)
; 2. that kp is tricking
;
vh.kwl: tstb @#kl.csr ; done, moni set ?
bpl klerr
mov #kl.ie,@#kl.csr ; clear moni
;
tst klcnt ; no kp check on first kl
beq 1$
tst kpcnt ; kwp ticking ?
beq kpold ; if not halt
;
1$: mov cbptr,r0 ; log kpcnt to trace buffer
mov kpcnt,(r0)+
cmp r0,#cbufe
blo 2$
mov #cbuf,r0
2$: mov r0,cbptr
clr kpcnt ; and finally clear
;
inc klcnt ; inc kl counter, prevent wrap
bne 900$
dec klcnt
900$: rti
;
klerr: halt
kpold: halt
;
; kw11-p interrupt handler ------------------------
; checks that
; 1. kp.mon is set (to detect spurious interrupts)
; 2. that kl is tricking (if kl stops, kpcnt saturates)
;
vh.kwp: tstb @#kp.csr ; done, moni set ?
bpl kperr
;
inc kpcnt ; inc kp counter, prevent wrap
beq klold ; if not also err halt
rti
;
kperr: halt
klold: halt
;
; data area ------------------------------------------------
;
buf: .blkb bsize
bufe:
;
klcnt: .word 0
kpcnt: .word 0
;
cbptr: .word cbuf
cbuf: .blkw cbsize
cbufe:
.end start

11
tools/tbench/w11a_hbpt/test_hbpt_basics.tcl
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@@ -1,10 +1,11 @@
# $Id: test_hbpt_basics.tcl 830 2016-12-26 20:25:49Z mueller $
# $Id: test_hbpt_basics.tcl 1138 2019-04-26 08:14:56Z mueller $
#
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-04-26 1138 1.0.3 leave system in clean state at end
# 2016-01-02 724 1.0.2 use s: defs for CP_STAT(rust)
# 2015-12-30 721 1.0.1 BUGFIX: add missing wtcpu in mfpd/mtpd tests
# 2015-07-11 700 1.0 Initial version
@@ -287,4 +288,8 @@ $cpu wtcpu -reset $rw11::asmwait_tout
$cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT dwseen] \
-rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \
-rpc -edata $sym(I7)
#
# be nice to later tests and reset cpu and hbpt unit
$cpu cp -stop \
-creset
rw11::hb_remove cpu0 0

173
tools/tbench/w11a_kw11p/test_kw11p_ctr.tcl
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@@ -1,10 +1,11 @@
# $Id: test_kw11p_ctr.tcl 1044 2018-09-15 11:12:07Z mueller $
# $Id: test_kw11p_ctr.tcl 1138 2019-04-26 08:14:56Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-04-24 1138 1.1 use loc access
# 2018-09-09 1044 1.0 Initial version
#
# Test ctr response with CSR(fix)
@@ -23,26 +24,26 @@ rlc log " A test basic counting -------------------------------------"
rlc log " A1: count down -------------------------------------"
# test with updn=0, avoid counter overflows
$cpu cp \
-wreg kwp.csb 0103 \
-rreg kwp.ctr -edata 0103 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix] \
-rreg kwp.ctr -edata 0102 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix] \
-rreg kwp.ctr -edata 0101 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix] \
-rreg kwp.ctr -edata 0100
-wma kwp.csb 0103 \
-rma kwp.ctr -edata 0103 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix] \
-rma kwp.ctr -edata 0102 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix] \
-rma kwp.ctr -edata 0101 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix] \
-rma kwp.ctr -edata 0100
rlc log " A1: count up ---------------------------------------"
# test with updn=1, avoid counter overflows
$cpu cp \
-wreg kwp.csb 0100 \
-rreg kwp.ctr -edata 0100 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rreg kwp.ctr -edata 0101 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rreg kwp.ctr -edata 0102 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rreg kwp.ctr -edata 0103
-wma kwp.csb 0100 \
-rma kwp.ctr -edata 0100 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rma kwp.ctr -edata 0101 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rma kwp.ctr -edata 0102 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rma kwp.ctr -edata 0103
# -- Section B ---------------------------------------------------------------
rlc log " B done response -------------------------------------------"
@@ -51,77 +52,77 @@ rlc log " B1: single count down to zero ----------------------"
# test with updn=0, count down to zero; check that read csr clears done
$cpu cp \
-wreg kwp.csb 3 \
-rreg kwp.ctr -edata 3 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix] \
-rreg kwp.ctr -edata 2 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix] \
-rreg kwp.ctr -edata 1 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix] \
-rreg kwp.ctr -edata 0 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR done] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR]
-wma kwp.csb 3 \
-rma kwp.ctr -edata 3 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix] \
-rma kwp.ctr -edata 2 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix] \
-rma kwp.ctr -edata 1 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix] \
-rma kwp.ctr -edata 0 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR done] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR]
rlc log " B2: single count up to zero ------------------------"
# test with updn=1, count up to zero; check that read csr clears done
$cpu cp \
-wreg kwp.csb 0177775 \
-rreg kwp.ctr -edata 0177775 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rreg kwp.ctr -edata 0177776 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rreg kwp.ctr -edata 0177777 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rreg kwp.ctr -edata 0 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR done updn] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn]
-wma kwp.csb 0177775 \
-rma kwp.ctr -edata 0177775 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rma kwp.ctr -edata 0177776 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rma kwp.ctr -edata 0177777 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn] \
-rma kwp.ctr -edata 0 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR done updn] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn]
rlc log " B3: repeat count down to zero ----------------------"
# test with updn=0 mode=1, repeat count down to zero
$cpu cp \
-wreg kwp.csb 2 \
-rreg kwp.ctr -edata 2 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 1 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 2 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR done mode] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 1 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 2 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR done mode] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR mode]
-wma kwp.csb 2 \
-rma kwp.ctr -edata 2 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 1 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 2 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR done mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 1 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 2 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR done mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR mode]
rlc log " B4: repeat count up to zero ------------------------"
# test with updn=1 mode=1, repeat count up to zero
$cpu cp \
-wreg kwp.csb 0177776 \
-rreg kwp.ctr -edata 0177776 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rreg kwp.ctr -edata 0177777 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn mode] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rreg kwp.ctr -edata 0177776 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR done updn mode] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn mode] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rreg kwp.ctr -edata 0177777 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn mode] \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rreg kwp.ctr -edata 0177776 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR done updn mode] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn mode]
-wma kwp.csb 0177776 \
-rma kwp.ctr -edata 0177776 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rma kwp.ctr -edata 0177777 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn mode] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rma kwp.ctr -edata 0177776 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR done updn mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn mode] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rma kwp.ctr -edata 0177777 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn mode] \
-wma kwp.csr [regbld rw11::KW11P_CSR fix updn mode] \
-rma kwp.ctr -edata 0177776 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR done updn mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn mode]
# -- Section C ---------------------------------------------------------------
rlc log " C err response --------------------------------------------"
@@ -130,15 +131,15 @@ rlc log " C1: repeat count down to zero ----------------"
# test with updn=0 mode=1, repeat count down to zero without csr read
$cpu cp \
-wreg kwp.csb 2 \
-rreg kwp.ctr -edata 2 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 1 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 2 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 1 \
-wreg kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rreg kwp.ctr -edata 2 \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR err done mode] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR mode]
-wma kwp.csb 2 \
-rma kwp.ctr -edata 2 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 1 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 2 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 1 \
-wma kwp.csr [regbld rw11::KW11P_CSR fix mode] \
-rma kwp.ctr -edata 2 \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR err done mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR mode]

12
tools/tbench/w11a_kw11p/test_kw11p_int.tcl
View File

@@ -1,4 +1,4 @@
# $Id: test_kw11p_int.tcl 1134 2019-04-21 17:18:03Z mueller $
# $Id: test_kw11p_int.tcl 1138 2019-04-26 08:14:56Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
@@ -42,7 +42,7 @@ stack:
start: spl 7 ; lock out interrupts
;
mov #2,@#kp.csb ; load kw11-p counter
mov #<kp.ie+kp.rhk+kp.run>,@#kp.csr ; setup: 100 kHz down single
mov #<kp.ie!kp.rhk!kp.run>,@#kp.csr ; setup: 100 kHz down single
spl 0 ; allow interrupts
mov #1000.,r0
1$: sob r0,1$ ; wait some time
@@ -82,7 +82,7 @@ start: spl 7 ; lock out interrupts
;
mov #3,r1 ; setup interrupt counter
mov #1,@#kp.csb ; load kw11-p counter
mov #<kp.ie+kp.rep+kp.rhk+kp.run>,@#kp.csr ; setup: 100 kHz dn rep
mov #<kp.ie!kp.rep!kp.rhk!kp.run>,@#kp.csr ; setup: 100 kHz dn rep
spl 0 ; allow interrupts
mov #1500.,r0
1$: sob r0,1$ ; wait some time
@@ -106,6 +106,10 @@ rlc log [format " 3 x 100 kHz ticks took %4d sob" [expr {1500-$reg0}]]
rlc log " B test interrupts via extevt=idec -------------------------"
rlc log " B1: repeat interrupt (mode=1) ----------------------"
# set erate to rext
$cpu cp \
-wibr kwp.csr [regbld rw11::KW11P_RCSR {erate "rext"}]
# setup three interrupts after 20 ticks of extevt counter
# wait loop will see
# 2(setup)+18(sob)+3(irupt)+17(sob)+3(irupt)+17(sob)+3(irupt+halt)
@@ -130,7 +134,7 @@ start: spl 7 ; lock out interrupts
;
mov #3,r1 ; setup interrupt counter
mov #20.,@#kp.csb ; load kw11-p counter
mov #<kp.ie+kp.rep+kp.rex+kp.run>,@#kp.csr ; setup: extevt dn rep
mov #<kp.ie!kp.rep!kp.rex!kp.run>,@#kp.csr ; setup: extevt dn rep
spl 0 ; allow interrupts
mov #70.,r0; ; timeout after 70 instructions
1$: sob r0,1$ ; wait some time

65
tools/tbench/w11a_kw11p/test_kw11p_regs.tcl
View File

@@ -1,10 +1,11 @@
# $Id: test_kw11p_regs.tcl 1045 2018-09-15 15:20:57Z mueller $
# $Id: test_kw11p_regs.tcl 1138 2019-04-26 08:14:56Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-04-24 1138 1.1 add csr.erate field test; use loc access
# 2018-09-15 1045 1.0 Initial version
# 2018-09-09 1044 0.1 First draft
#
@@ -24,23 +25,51 @@ rlc log " A basic register access tests -----------------------------"
rlc log " A1: write/read csr ---------------------------------"
# test that ie,updn,mode and rate are write/readable; done,err not writable
$cpu cp \
-wreg kwp.csr [regbld rw11::KW11P_CSR ie] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR ie] \
-wreg kwp.csr [regbld rw11::KW11P_CSR updn] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR updn] \
-wreg kwp.csr [regbld rw11::KW11P_CSR mode] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wreg kwp.csr [regbld rw11::KW11P_CSR {rate "rext"}] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR {rate "rext"}] \
-wreg kwp.csr [regbld rw11::KW11P_CSR err done mode] \
-rreg kwp.csr -edata [regbld rw11::KW11P_CSR mode]
-wma kwp.csr [regbld rw11::KW11P_CSR ie] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR ie] \
-wma kwp.csr [regbld rw11::KW11P_CSR updn] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR updn] \
-wma kwp.csr [regbld rw11::KW11P_CSR mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR mode] \
-wma kwp.csr [regbld rw11::KW11P_CSR {rate "rext"}] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR {rate "rext"}] \
-wma kwp.csr [regbld rw11::KW11P_CSR err done mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR mode]
rlc log " A2: read/write erate -------------------------------"
# test that erate is rem writable, but not the other fields
$cpu cp \
-wma kwp.csr [regbld rw11::KW11P_CSR ie mode] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR ie mode] \
-wibr kwp.csr [regbld rw11::KW11P_RCSR {erate "usec"}] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR ie mode] \
-ribr kwp.csr -edata [regbld rw11::KW11P_RCSR {erate "usec"} ie mode]
rlc log " A3: write csb, read ctr ----------------------------"
# write csb, check csb reads 0, ctr returns csb value, and ctr write is noop
$cpu cp \
-wreg kwp.csr 0x0000 \
-wreg kwp.csb 0xbeaf \
-rreg kwp.csb -edata 0x0000 \
-rreg kwp.ctr -edata 0xbeaf \
-wreg kwp.ctr 0xdead \
-rreg kwp.ctr -edata 0xbeaf
-wma kwp.csr 0x0000 \
-wma kwp.csb 0xbeaf \
-rma kwp.csb -edata 0x0000 \
-rma kwp.ctr -edata 0xbeaf \
-wma kwp.ctr 0xdead \
-rma kwp.ctr -edata 0xbeaf
rlc log " A4: test breset ------------------------------------"
# all csr fields a cleared, only erate (hidden and rem only) stays
$cpu cp \
-wma kwp.csr [regbld rw11::KW11P_CSR ie updn mode {rate "r10k"}] \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR ie updn mode {rate "r10k"}] \
-wibr kwp.csr [regbld rw11::KW11P_RCSR {erate "rext"}] \
-ribr kwp.csr -edata [regbld rw11::KW11P_RCSR {erate "rext"} \
ie updn mode {rate "r10k"}] \
-breset \
-rma kwp.csr -edata [regbld rw11::KW11P_CSR {rate "r100k"}] \
-ribr kwp.csr -edata [regbld rw11::KW11P_RCSR {erate "rext"} {rate "r100k"}]
# harvest breset/creset triggered attn's
rlc exec -attn
rlc wtlam 0.
# finally set erate to scnt (the default) again
$cpu cp \
-wibr kwp.csr [regbld rw11::KW11P_RCSR {erate "sclk"}] \
-ribr kwp.csr -edata [regbld rw11::KW11P_RCSR {erate "sclk"} {rate "r100k"}]

11
tools/tcl/rw11/defs.tcl
View File

@@ -1,4 +1,4 @@
# $Id: defs.tcl 1121 2019-03-11 08:59:12Z mueller $
# $Id: defs.tcl 1138 2019-04-26 08:14:56Z mueller $
#
# Copyright 2014-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2019-04-24 1138 1.0.8 add RCSR defs for KW11-L and KW11-P
# 2019-03-10 1121 1.0.7 define INIT bits; define ANUM
# 2018-09-09 1044 1.0.6 update defs kw11p, literals for KW11P_CSR(rate)
# 2017-02-17 851 1.0.5 defs for auxilliary devices (kw11l,kw11p,iist)
@@ -121,7 +122,8 @@ namespace eval rw11 {
# KW11-L line clock
set A_KW11L_CSR 0177546
regdsc KW11L_CSR {moni 7} {ie 6}
rw11util::regmap_add rw11 kwl.csr {?? KW11L_CSR}
regdsc KW11L_RCSR {moni 7} {ie 6} {ir 5}
rw11util::regmap_add rw11 kwl.csr {l? KW11L_CSR r? KW11L_RCSR}
#
# KW11-P line clock
set A_KW11P_CSR 0172540
@@ -129,7 +131,10 @@ namespace eval rw11 {
set A_KW11P_CTR 0172544
regdsc KW11P_CSR {err 15} {done 7} {ie 6} {fix 5} {updn 4} {mode 3} \
{rate 2 2 "s:r100k:r10k:rline:rext"} {run 0}
rw11util::regmap_add rw11 kwp.csr {?? KW11P_CSR}
regdsc KW11P_RCSR {err 15} {ir 10} {erate 9 2 "s:sclk:usec:rext:noop"} \
{done 7} {ie 6} {fix 5} {updn 4} {mode 3} \
{rate 2 2 "s:r100k:r10k:rline:rext"} {run 0}
rw11util::regmap_add rw11 kwp.csr {l? KW11P_CSR r? KW11P_RCSR}
#
# IIST - interprocessor communication
set A_IIST_ACR 0177500