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BUGFIX: cc state unchanged after abort - dstw case
- rtl/w11a/ - pdp11_psr.vhd: BUGFIX: inhibit CCWE when PSW being written - pdp11_sequencer.vhd: BUGFIX: cc state unchanged after abort - tools - bin/tmuconv: fix ru header - gwstart/lib/psr.tcl: added, definitions for psr - tcode/cpu_details.mac: update A4.1, add B3.1 Closes #37
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wfjm
@@ -1,4 +1,4 @@
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; $Id: cpu_details.mac 1337 2022-12-26 11:14:21Z mueller $
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; $Id: cpu_details.mac 1340 2023-01-01 08:43:05Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -9,7 +9,7 @@
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;
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; Test CPU details
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; Section A: CPU registers
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; Section B: stress tests
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; Section B: stress and flow tests
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; Section C: 11/70 specifics
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;
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.include |lib/tcode_std_base.mac|
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@@ -86,7 +86,7 @@
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; A4.3 RTI/RTT tbit basics
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; part 1: tbit after RTI
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; part 2: tbit after RTT
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; A4.4 Test A4.4 -- tbit trace tests
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; A4.4 tbit trace tests
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; part 0: traced TRAP that clears tbit
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; part 1: simple instruction sequence
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; part 2: tracing of trap instructions (EMT tested)
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@@ -927,6 +927,8 @@ ta0305: cmpb systyp,#sy.sih ; skip in SimH (different stklim logic)
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ta0401:
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;
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; part 1: all bits except register set (cp.ars) ----------------------
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; Note: In a direct PSW write the cc of the write prevail.
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; This part tests dstw flow via MOV. Part 4 will test dstr flow.
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;
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mov #cp.psw,r0 ; ptr to PSW
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mov #200$,r1 ; ptr to data
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@@ -934,14 +936,16 @@ ta0401:
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100$: mov (r1)+,r3 ; next value
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beq 2000$ ; if 0 end of test
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mov r3,(r0) ; write PSW
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mov (r0),r3 ; read PSW
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bic r2,r3 ; clear NZVC
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cmp (r1)+,r3 ; check value
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cmp (r0),(r1)+ ; check PSW
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beq 100$
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clr (r0) ; if error force kernel
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halt ; and halt
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;
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200$: .word cp.t,0 ; tbit (not direct writable)
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200$: .word cp.c,cp.c ; C cc
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.word cp.v,cp.v ; V cc
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.word cp.z,cp.z ; Z cc
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.word cp.n,cp.n ; N cc
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.word cp.t,0 ; tbit (not direct writable)
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.word cp.pr7,cp.pr7 ; prio bits
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.word bit10!bit09!bit08,0 ; bit 10:8 unused
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.word bit12,bit12 ; pm(0)
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@@ -952,7 +956,8 @@ ta0401:
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;
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; part 2: PSW(11) - register set -------------------------------------
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;
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2000$: mov #1000,r0 ; write to set 0
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2000$: clr cp.psw ; select set 0
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mov #1000,r0 ; write to set 0
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mov #1001,r1
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mov #1002,r2
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mov #1003,r3
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@@ -1005,6 +1010,21 @@ ta0401:
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clr (r0)
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mov #stack,sp
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;
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; part 4: verify PSW manipulation via BIS and BIC
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; Note: In a direct PSW write the cc of the write prevail.
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;
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mov #cp.psw,r0 ; ptr to PSW
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ccc
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bis #cp.n!cp.c,(r0) ; set N+C
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hcmpeq #cpn00c,(r0)
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ccc
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bis #cp.pr7!cp.z!cp.v,(r0) ; set PRI=7,Z+V
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hcmpeq #cp.pr7!cp0zv0,(r0)
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scc
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bic #cp.z!cp.v,(r0) ; clr Z+V
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hcmpeq #cp.pr7!cpn00c,(r0)
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clr (r0) ; back to normal
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;
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9999$: iot ; end of test A4.1
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;
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; Test A4.2 -- PSW write/read via RTI/RTT ++++++++++++++++++++++++++++
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@@ -1514,14 +1534,20 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler
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;
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9999$: iot ; end of test A4.4
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;
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; Section B: Stress tests ====================================================
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; Section B: Stress and fllow tests ==========================================
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; B1 address mode torture tests
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; B1.1 src-dst update hazards with (r0)+,(r0)
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; B1.2 (pc)+ as destination
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; B1.3 pc as destination in clr, mov, and add
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; B2 pipeline torture tests
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; B2.1 self-modifying code, use (pc), -(pc)
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; B2.2 self-modifying code, use (pc) case 2
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; B2.1 self-modifying code, use (pc), -(pc)
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; B2.2 self-modifying code, use (pc) case 2
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; B3 specifier flow tests
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; B3.1 dstw flow and cc
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; part 1: check cc for MOV for all modes
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; part 2: check cc for CLR for all modes
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; part 3: check cc for SXT for all modes
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; part 4: check cc for MOV after abort for all modes
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;
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; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
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; This sub-section tests peculiar address node usage
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@@ -1677,6 +1703,135 @@ tb0202: mov #2,r5
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;
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9999$: iot ; end of test B2.2
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;
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; Test B3: specifier flow tests +++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section tests flow and cc properties
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;
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; Test B3.1 -- dstw flow and cc ++++++++++++++++++++++++++++++++++++++
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;
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tb0301: mov #123,r0 ; src for MOV
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mov #100$,r1 ; dst for (r1),(r1)+,-(r1),0(r1)
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mov #200$,r2 ; dst for @(r2)+,@-(r2),@0(r2)
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mov #cp.psw,r3 ; ptr to PSW
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br 1000$
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;
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100$: .word 0 ; dst target
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200$: .word 100$ ; ptr to dst
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300$: .word 1 ; odd address ptr
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;
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; part 1: check cc for MOV for all modes
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;
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1000$: scc
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mov r0,r4 ; mode 0
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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scc
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mov r0,(r1) ; mode 1
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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scc
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mov r0,(r1)+ ; mode 2
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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scc
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mov r0,-(r1) ; mode 4
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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scc
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mov r0,0(r1) ; mode 6
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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scc
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mov r0,@(r2)+ ; mode 3
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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scc
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mov r0,@-(r2) ; mode 5
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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scc
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mov r0,@0(r2) ; mode 7
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hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
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;
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; part 2: check cc for CLR for all modes
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;
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2000$: scc
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clr r4 ; mode 0
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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scc
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clr (r1) ; mode 1
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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scc
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clr (r1)+ ; mode 2
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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scc
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clr -(r1) ; mode 4
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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scc
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clr 0(r1) ; mode 6
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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scc
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clr @(r2)+ ; mode 3
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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scc
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clr @-(r2) ; mode 5
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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scc
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clr @0(r2) ; mode 7
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hcmpeq #cp0z00,(r3) ; N=0,Z=1,V=0,C=0
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;
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; part 3: check cc for SXT for all modes
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;
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3000$: scc
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sxt r4 ; mode 0
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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scc
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sxt (r1) ; mode 1
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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scc
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sxt (r1)+ ; mode 2
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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scc
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sxt -(r1) ; mode 4
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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scc
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sxt 0(r1) ; mode 6
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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scc
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sxt @(r2)+ ; mode 3
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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scc
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sxt @-(r2) ; mode 5
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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scc
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sxt @0(r2) ; mode 7
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hcmpeq #cpn00c,(r3) ; Z=0,V=0 and keep N,C
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;
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; part 4: check cc for MOV after abort for all memory modes
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; Notes:
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; - w11 updates the cc state after possible address errors
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; - SimH updates the cc state before possible address errors
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;
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4000$: cmpb systyp,#sy.sih ; skip on SimH
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beq 9999$
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clr r5 ; abort counter
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mov #4100$,v..iit ; set up iit handler
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mov #1,r1 ; odd dst for (r1),(r1)+,-(r1),0(r1)
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mov #300$,r2 ; odd dst for @(r2)+,@-(r2),@0(r2)
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scc
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;
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mov r0,(r1) ; mode 1
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mov r0,(r1)+ ; mode 2
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mov #3,r1 ; restore r1
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scc
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mov r0,-(r1) ; mode 4
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mov r0,0(r1) ; mode 6
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mov r0,@(r2)+ ; mode 3
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mov r0,@-(r2) ; mode 5
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mov r0,@0(r2) ; mode 7
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br 4200$
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;
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4100$: inc r5 ; bump counter
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hcmpeq #cpnzvc,2(sp) ; PS cc untouched !!
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rti ; continue (possible here!)
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;
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4200$: hcmpeq #7.,r5 ; check that all 7 mov get address error
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mov #v..iit+2,v..iit ; restore
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;
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9999$: iot ; end of test B3.1
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;
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; Section C: 11/70 specifics =================================================
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; C1 Implementation differences
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; C1.1 Register used as source and changed in dst flow
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@@ -1735,7 +1890,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#29. ; all tests done ?
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hcmpeq tstno,#30. ; all tests done ?
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;
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jmp loop
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;
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