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cpu_basics.mac: add JSR, MARK, SPL, RESET
This commit is contained in:
wfjm
4
tools/tcode/.gitignore
vendored
4
tools/tcode/.gitignore
vendored
@@ -1,7 +1,11 @@
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*.cof
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*.lst
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*.lsm
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*.lsm_scmd
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# simulation stuff
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rlink_cext_conf
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rlink_cext_fifo_rx
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rlink_cext_fifo_tx
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sysmon_stim
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tmu_ofile
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@@ -1,4 +1,4 @@
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; $Id: cpu_basics.mac 1253 2022-07-12 06:32:22Z mueller $
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; $Id: cpu_basics.mac 1259 2022-07-18 17:39:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -7,9 +7,16 @@
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; 2022-07-11 1253 1.0 Initial version
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; 2015-08-30 710 0.1 First draft
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;
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; Test CPU basics
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; Test CPU basics: most instructions except traps, EIS and FPP
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; Section A: ccops + flow control bxx, sob, jmp, jsr, rts, mark
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; Section B: unary instructions (word)
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; Section C: binary instructions (word)
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; Section D: unary instructions (byte)
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; Section E: binary instructions (byte)
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; Section F: miscellaneous (spl, reset)
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;
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.include |lib/tcode_std_base.mac|
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.include |lib/defs_kwl.mac|
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;
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; Section A: ccops + flow control bxx, sob, jmp, jsr, rts, mark ==============
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;
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@@ -872,6 +879,200 @@ ta0302: mov #cp.psw,r5
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;
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9999$: iot ; end of test A3.2
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;
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; Test A4 -- jsr + rts +++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 000 100 rrr ddd ddd ---- JSR (mode /= R !!)
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; 0 000 000 010 000 rrr ---- RTS
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;
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; Test A4.1 -- jsr + dsta +++++++++++++++++++++++++++++++++++++++++++++
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; check that JSR PC,xxx works for all modes
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;
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ta0401: mov #1006$,r2
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mov #2000$,r3
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mov #3000$,r5
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clr r4
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;
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jsr pc,(r2)+ ; mode = 2,reg -> 1006 inc 6
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jsr pc,(r2) ; mode = 1,reg -> 1005 inc 5
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jsr pc,2(r2) ; mode = 6,reg -> 1004 inc 4
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jsr pc,-(r2) ; mode = 4,reg -> 1006 inc 6
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jsr pc,@(r3)+ ; mode = 3,reg -> 1003 inc 3
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jsr pc,@2(r3) ; mode = 7,reg -> 1001 inc 1
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jsr pc,@-(r3) ; mode = 5,reg -> 1003 inc 3
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;
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jmp 9999$
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;
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1006$: inc r4
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1005$: inc r4
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1004$: inc r4
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1003$: inc r4
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1002$: inc r4
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1001$: inc r4
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cmp r4,(r5)+
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beq .+4
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halt
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rts pc
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;
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2000$: .word 1003$
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.word 1002$
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.word 1001$
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;
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3000$: .word 6
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.word 6+5
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.word 6+5+4
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.word 6+5+4+6
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.word 6+5+4+6+3
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.word 6+5+4+6+3+1
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.word 6+5+4+6+3+1+3
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;
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9999$: iot ; end of test A4.1
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;
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; Test A4.2 -- jsr + cc +++++++++++++++++++++++++++++++++++++++++++++++
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; check that JSR and RTS doesnt change cc
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;
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ta0402: mov #cp.psw,r5
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clr (r5)
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;
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ccc ; nzvc = 0000
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jsr pc,100$ ; call with cp0000
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cmp (r5),#cpnzvc ; expect cpnzvc
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beq .+4
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halt
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scc
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jsr pc,200$
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cmp (r5),#cp0000
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beq .+4
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halt
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jmp 9999$
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;
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100$: cmp (r5),#cp0000 ; expect cp0000
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beq .+4
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halt
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scc ; return with cpnzvc
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rts pc
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;
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200$: cmp (r5),#cpnzvc ; expect cpnzvc
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beq .+4
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halt
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ccc ; return with cp0000
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rts pc
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;
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9999$: iot ; end of test A4.2
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;
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; Test A4.3 -- jsr r0-r5 ++++++++++++++++++++++++++++++++++++++++++++++
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; check that JSR and RTS for R0...R5 linkage
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; Note: use reserved opcodes as arguments to detect fall through
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;
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ta0403: clr 900$ ; reset call counter
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jsr r0,100$
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jsr r1,110$
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.word 000211
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jsr r2,120$
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.word 000212
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jsr r3,130$
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.word 000213
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jsr r4,140$
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.word 000214
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jsr r5,150$
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.word 000215
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.word 000216
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.word 000217
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cmp 900$,#6. ; check number of calls
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beq .+4
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halt
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jmp 9999$
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;
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100$: inc 900$
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rts r0
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;
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110$: inc 900$
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cmp (r1)+,#000211
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beq .+4
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halt
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rts r1
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;
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120$: inc 900$
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cmp (r2)+,#000212
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beq .+4
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halt
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rts r2
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;
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130$: inc 900$
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cmp (r3)+,#000213
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beq .+4
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halt
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rts r3
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;
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140$: inc 900$
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cmp (r4)+,#000214
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beq .+4
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halt
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rts r4
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;
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150$: inc 900$
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cmp (r5)+,#000215
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beq .+4
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halt
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cmp (r5)+,#000216
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beq .+4
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halt
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cmp (r5)+,#000217
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beq .+4
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halt
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rts r5
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;
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900$: .word 0
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;
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9999$: iot ; end of test A4.3
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;
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; Test A5 -- mark ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 000 110 100 nnn nnn ---- MARK
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;
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; Test A5.1 -- mark +++++++++++++++++++++++++++++++++++++++++++++++++++
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; check that MARK works
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; Note: this instruction is a bastard, the only PDP-11 instruction which
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; is outright ugly and should have neven been invented.
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; Not used in all surviving OS so this test is most likely the only
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; occasion where MARK is executed on a target system.
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;
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ta0501: mov #123456,r5 ; token
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mov r5,-(sp) ; from here processor handbook example
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mov #101,-(sp) ; push 1st parameter
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mov #102,-(sp) ; push 2nd parameter
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mov #103,-(sp) ; push 3rd parameter
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mov #<mark+3>,-(sp) ; push MARK 3
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mov sp,r5 ; push address of MARK 3
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jsr pc,100$ ; call procedure
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cmp r5,#123456 ; check token
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beq .+4
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halt
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jmp 9999$
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;
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; stack of procedure when called:
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; content
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; 12(sp) 10(r5) old r5
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; 10(sp) 6(r5) param1
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; 6(sp) 4(r5) param2
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; 4(sp) 2(r5) param3
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; 2(sp) (r5) mark 3
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; (sp) return pc
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;
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100$: cmp 6(r5),#101 ; check 1st parameter
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beq .+4
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halt
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cmp 4(r5),#102 ; check 2nd parameter
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beq .+4
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halt
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cmp 2(r5),#103 ; check 3rd parameter
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beq .+4
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halt
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rts r5 ; return
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;
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9999$: iot ; end of test A5.1
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;
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; Section B: unary instructions (word) =======================================
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;
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jmp tb0101
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@@ -2790,11 +2991,178 @@ te0501: clr cp.psw
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;
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9999$: iot ; end of test E5.1
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;
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; Section F: miscellaneous (spl, reset) ======================================
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;
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; Test F1: spl ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 000 000 010 011 nnn ---- SPL
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;
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; Test F1.1 -- spl in kernel mode ++++++++++++++++++++++++++++++++++++
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; Test that PSW is changed
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;
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tf0101: mov #cp.psw,r0
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clr (r0)
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;
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ccc
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sen
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spl 1
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cmp (r0),#<cp.pr1+cpn000>
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beq .+4
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halt
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;
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ccc
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sez
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spl 2
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cmp (r0),#<cp.pr2+cp0z00>
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beq .+4
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halt
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;
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ccc
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sev
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spl 3
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cmp (r0),#<cp.pr3+cp00v0>
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beq .+4
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halt
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;
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ccc
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sec
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spl 4
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cmp (r0),#<cp.pr4+cp000c>
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beq .+4
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halt
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;
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scc
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cln
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spl 5
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cmp (r0),#<cp.pr5+cp0zvc>
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beq .+4
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halt
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;
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scc
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clz
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spl 6
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cmp (r0),#<cp.pr6+cpn0vc>
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beq .+4
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halt
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;
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scc
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clv
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spl 7
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cmp (r0),#<cp.pr7+cpnz0c>
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beq .+4
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halt
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;
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scc
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clc
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spl 0
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cmp (r0),#<cp.pr0+cpnzv0>
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beq .+4
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halt
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;
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9999$: iot ; end of test F1.1
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;
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; Test F1.2 -- spl in supervisor and user mode +++++++++++++++++++++++
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; Test that SPL is nop when not in kernel mode
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;
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tf0102: mov #cp.psw,r0
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;
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mov #cp.cms,(r0) ; to supervisor mode
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ccc
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spl 4
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cmp (r0),#<cp.cms+cp.pr0+cp0000>
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beq .+4
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halt
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;
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mov #cp.cmu,(r0) ; to user mode
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scc
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spl 5
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cmp (r0),#<cp.cmu+cp.pr0+cpnzvc>
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beq .+4
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halt
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;
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clr (r0) ; back to kernel mode
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;
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9999$: iot ; end of test F1.2
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;
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; Test F2: reset ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 000 000 000 000 101 ---- RESET
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;
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; Test F2.1 -- reset in kernel mode ++++++++++++++++++++++++++++++++++
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; This test checks whether
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; - KW11-L line clock csr is cleared (representing all devices)
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; - PIRQ is cleared
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; - STKLIM is cleared
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; Effect on MMR0 and MMR3 is tested in MMU test
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;
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tf0201: mov #cp.psw,r0
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mov #cp.pr7,(r0) ; lock-out interrupts
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mov #kl.ie,kl.csr ; enable KW11-L interrupt
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bit #kl.ie,kl.csr ; check that kl.ie bit is set
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bne .+4
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halt
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movb #bit01,cp.pir+1 ; set PIRQ bit
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cmpb #bit01,cp.pir+1 ; check
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beq .+4
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halt
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mov #400,cp.sli ; bump STKLIM
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cmp #400,cp.sli ; check
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beq .+4
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halt
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;
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reset ; and RESET
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bit #kl.ie,kl.csr ; check that kl.ie bit is cleared
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beq .+4
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halt
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tstb cp.pir+1 ; check that PIRQ cleared
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beq .+4
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halt
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tst cp.sli ; check that STKLIM cleared
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beq .+4
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halt
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ccc ; clear cc
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cmp (r0),#cp.pr7 ; check that prio still 7 (CPU not(!) reset)
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beq .+4
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halt
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clr (r0) ; back to normal
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;
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9999$: iot ; end of test F2.1
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;
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; Test F2.2 -- reset in supervisor and user mode +++++++++++++++++++++
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; This test checks whether
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; - KW11-L line clock csr is not(!) cleared (representing all devices)
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;
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tf0202: mov #cp.psw,r0
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mov #cp.pr7,(r0) ; lock-out interrupts
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mov #kl.ie,kl.csr ; enable KW11-L interrupt
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;
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mov #<cp.cms+cp.pr7>,(r0) ; supervisor mode, keep pr7 !
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reset ; and RESET
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bit #kl.ie,kl.csr ; check that bit is set
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bne .+4
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halt
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;
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mov #<cp.cmu+cp.pr7>,(r0) ; user mode, keep pr7 !
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reset ; and RESET
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bit #kl.ie,kl.csr ; check that bit is set
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bne .+4
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halt
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;
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mov #<cp.pr7>,(r0) ; kernel mode, keep pr7 !
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clr kl.csr ; disable KW11-L interrupt
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clr (r0) ; back to normal
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;
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9999$: iot ; end of test F2.2
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;
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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cmp tstno,#43. ; all tests done ?
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cmp tstno,#51. ; all tests done ?
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beq .+4
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halt
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;
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jmp loop
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;
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.end start
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