comment changes

rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd

@@ -1,4 +1,4 @@
--- $Id: fx2_2fifoctl_ic.vhd 890 2017-04-30 15:27:53Z mueller $
+-- $Id: fx2_2fifoctl_ic.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2012-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -13,7 +13,7 @@
 -- 
 ------------------------------------------------------------------------------
 -- Module Name:    fx2_2fifoctl_ic - syn
--- Description:    Cypress EZ-USB FX2 driver (2 fifo; int clk)
+-- Description:    Cypress EZ-USB FX2 controller (2 fifo; int clk)
 --
 -- Dependencies:   vlib/xlib/iob_reg_o
 --                 vlib/xlib/iob_reg_i_gen
@@ -52,7 +52,7 @@ use work.xlib.all;
 use work.memlib.all;
 use work.fx2lib.all;
 
-entity fx2_2fifoctl_ic is               -- EZ-USB FX2 driver (2 fifo; int clk)
+entity fx2_2fifoctl_ic is               -- EZ-USB FX2 controller(2 fifo; int clk)
   generic (
     RXFAWIDTH : positive :=  5;         -- receive  fifo address width
     TXFAWIDTH : positive :=  5;         -- transmit fifo address width

rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd

@@ -1,4 +1,4 @@
--- $Id: fx2_3fifoctl_ic.vhd 890 2017-04-30 15:27:53Z mueller $
+-- $Id: fx2_3fifoctl_ic.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2012-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -13,7 +13,7 @@
 -- 
 ------------------------------------------------------------------------------
 -- Module Name:    fx2_3fifoctl_ic - syn
--- Description:    Cypress EZ-USB FX2 driver (3 fifo; int clk)
+-- Description:    Cypress EZ-USB FX2 controller (3 fifo; int clk)
 --
 -- Dependencies:   vlib/xlib/iob_reg_o
 --                 vlib/xlib/iob_reg_i_gen
@@ -49,7 +49,7 @@ use work.xlib.all;
 use work.memlib.all;
 use work.fx2lib.all;
 
-entity fx2_3fifoctl_ic is               -- EZ-USB FX2 driver (3 fifo; int clk)
+entity fx2_3fifoctl_ic is               -- EZ-USB FX2 controller(3 fifo; int clk)
   generic (
     RXFAWIDTH : positive :=  5;         -- receive  fifo address width
     TXFAWIDTH : positive :=  5;         -- transmit fifo address width

rtl/bplib/fx2lib/fx2lib.vhd

@@ -1,4 +1,4 @@
--- $Id: fx2lib.vhd 888 2017-04-30 13:06:51Z mueller $
+-- $Id: fx2lib.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2011-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -76,7 +76,7 @@ package fx2lib is
 
 
 -- -------------------------------------
-component fx2_2fifoctl_ic is            -- EZ-USB FX2 driver (2 fifo; int clk)
+component fx2_2fifoctl_ic is            -- EZ-USB FX2 controller(2 fifo; int clk)
   generic (
     RXFAWIDTH : positive :=  5;         -- receive  fifo address width
     TXFAWIDTH : positive :=  5;         -- transmit fifo address width
@@ -107,7 +107,7 @@ component fx2_2fifoctl_ic is            -- EZ-USB FX2 driver (2 fifo; int clk)
   );
 end component;
 
-component fx2_3fifoctl_ic is            -- EZ-USB FX2 driver (3 fifo; int clk)
+component fx2_3fifoctl_ic is            -- EZ-USB FX2 controller(3 fifo; int clk)
   generic (
     RXFAWIDTH : positive :=  5;         -- receive  fifo address width
     TXFAWIDTH : positive :=  5;         -- transmit fifo address width

rtl/bplib/nexys2/nexys2lib.vhd

@@ -1,4 +1,4 @@
--- $Id: nexys2lib.vhd 649 2015-02-21 21:10:16Z mueller $
+-- $Id: nexys2lib.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -23,7 +23,7 @@
 -- 2013-01-01   467   1.4    add nexys2_cuff_aif, nexys2_fusp_cuff_aif
 -- 2011-12-23   444   1.3    remove clksys output hack
 -- 2011-11-26   433   1.2    remove n2_cram_* modules, now in nxcramlib
--- 2011-11-23   432   1.1    remove O_FLA_CE_N port in cram driver/dummy
+-- 2011-11-23   432   1.1    remove O_FLA_CE_N port in cram controller/dummy
 -- 2010-11-13   338   1.0.2  add O_CLKSYS to aif's (DCM derived system clock)
 -- 2010-11-06   336   1.0.4  rename input pin CLK -> I_CLK50
 -- 2010-05-28   295   1.0.3  use _ADV_N also for n2_cram_dummy

rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd

@@ -1,4 +1,4 @@
--- $Id: nx_cram_memctl_as.vhd 907 2017-06-05 08:19:12Z mueller $
+-- $Id: nx_cram_memctl_as.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -13,7 +13,7 @@
 -- 
 ------------------------------------------------------------------------------
 -- Module Name:    nx_cram_memctl_as - syn
--- Description:    nexys2/3/4: CRAM driver - async and page mode
+-- Description:    nexys2/3/4: CRAM controller - async and page mode
 --
 -- Dependencies:   vlib/xlib/iob_reg_o
 --                 vlib/xlib/iob_reg_o_gen
@@ -117,7 +117,7 @@ use ieee.numeric_std.all;
 use work.slvtypes.all;
 use work.xlib.all;
 
-entity nx_cram_memctl_as is             -- CRAM driver (async+page mode)
+entity nx_cram_memctl_as is             -- CRAM controller (async+page mode)
   generic (
     READ0DELAY : positive := 4;         -- read word 0 delay in clock cycles
     READ1DELAY : positive := 2;         -- read word 1 delay in clock cycles

rtl/bplib/nxcramlib/nxcramlib.vhd

@@ -1,4 +1,4 @@
--- $Id: nxcramlib.vhd 788 2016-07-16 22:23:23Z mueller $
+-- $Id: nxcramlib.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -13,7 +13,7 @@
 --
 ------------------------------------------------------------------------------
 -- Package Name:   nxcramlib
--- Description:    Nexys 2/3 CRAM drivers
+-- Description:    Nexys 2/3 CRAM controllers
 -- 
 -- Dependencies:   -
 -- Tool versions:  ise 11.4-14.7; viv 2014.4-2016.2; ghdl 0.26-0.33
@@ -56,7 +56,7 @@ component nx_cram_dummy is              -- CRAM protection dummy
   );
 end component;
 
-component nx_cram_memctl_as is          -- CRAM driver (async+page mode)
+component nx_cram_memctl_as is          -- CRAM controller (async+page mode)
   generic (
     READ0DELAY : positive := 4;         -- read word 0 delay in clock cycles
     READ1DELAY : positive := 2;         -- read word 1 delay in clock cycles

rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd

@@ -1,4 +1,4 @@
--- $Id: tb_nx_cram_memctl.vhd 802 2016-08-27 19:00:23Z mueller $
+-- $Id: tb_nx_cram_memctl.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -47,7 +47,7 @@ end tb_nx_cram_memctl;
 
 architecture sim of tb_nx_cram_memctl is
   
-component tbd_nx_cram_memctl is         -- CRAM driver (abstract) [tb design]
+component tbd_nx_cram_memctl is         -- CRAM controller (abstract) [tb design]
   port (
     CLK : in slbit;                     -- clock
     RESET : in slbit;                   -- reset

rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd

@@ -1,4 +1,4 @@
--- $Id: tbd_nx_cram_memctl_as.vhd 802 2016-08-27 19:00:23Z mueller $
+-- $Id: tbd_nx_cram_memctl_as.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -43,7 +43,7 @@ use ieee.std_logic_1164.all;
 use work.slvtypes.all;
 use work.nxcramlib.all;
 
-entity tbd_nx_cram_memctl_as is         -- CRAM driver (async mode) [tb design]
+entity tbd_nx_cram_memctl_as is         -- CRAM controller (async mode) [tb wrap]
                                         -- generic: READ0=2;READ1=2;WRITE=3
   port (
     CLK : in slbit;                     -- clock

rtl/bplib/s3board/s3boardlib.vhd

@@ -1,4 +1,4 @@
--- $Id: s3boardlib.vhd 649 2015-02-21 21:10:16Z mueller $
+-- $Id: s3boardlib.vhd 911 2017-06-11 10:52:32Z mueller $
 --
 -- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -99,7 +99,7 @@ component s3_sram_dummy is              -- SRAM protection dummy
   );
 end component;
 
-component s3_sram_memctl is             -- SRAM driver
+component s3_sram_memctl is             -- SRAM controller
   port (
     CLK : in slbit;                     -- clock
     RESET : in slbit;                   -- reset

rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd

@@ -1,4 +1,4 @@
--- $Id: sys_tst_snhumanio_b3.vhd 640 2015-02-01 09:56:53Z mueller $
+-- $Id: sys_tst_snhumanio_b3.vhd 907 2017-06-05 08:19:12Z mueller $
 --
 -- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,9 +22,9 @@
 -- Test bench:     -
 --
 -- Target Devices: generic
--- Tool versions:  viv 2014.4; ghdl 0.31
+-- Tool versions:  viv 2014.4-2016.4; ghdl 0.31-0.34
 --
--- Synthesized (xst):
+-- Synthesized (viv):
 -- Date         Rev  viv    Target       flop  lutl  lutm  bram  slic
 -- 2015-01-30   636 2014.4  xc7a35t-1     154   133     0     0    63  
 --

rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4.vhd

@@ -1,4 +1,4 @@
--- $Id: tb_tst_sram_n4.vhd 643 2015-02-07 17:41:53Z mueller $
+-- $Id: tb_tst_sram_n4.vhd 912 2017-06-11 18:30:03Z mueller $
 --
 -- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -13,7 +13,7 @@
 --
 ------------------------------------------------------------------------------
 -- Module Name:    tb_tst_sram_n4
--- Description:    Configuration for tb_tst_sram_n4 for tb_nexys4_fusp
+-- Description:    Configuration for tb_tst_sram_n4 for tb_nexys4_cram
 --
 -- Dependencies:   sys_tst_sram_n4
 --