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add and use rbaddr_ constants; use x"0000" notation

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This commit is contained in:
wfjm
2019-06-09 11:22:52 +02:00
parent 07909777df
commit c575613867
33 changed files with 169 additions and 133 deletions
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18
rtl/bplib/bpgen/bpgenrbuslib.vhd
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@@ -1,6 +1,6 @@
-- $Id: bpgenrbuslib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: bpgenrbuslib.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2013-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,7 +16,7 @@
-- Description: Generic Board/Part components using rbus
--
-- Dependencies: -
-- Tool versions: ise 12.1-14.7; viv 2014.4-2017.1; ghdl 0.26-0.34
-- Tool versions: ise 12.1-14.7; viv 2014.4-2019.1; ghdl 0.26-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.3.2 add sn_humanio_emu_rbus
@@ -35,14 +35,14 @@ use work.slvtypes.all;
use work.rblib.all;
package bpgenrbuslib is
component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -65,7 +65,7 @@ component sn_humanio_rbus is -- human i/o handling /w rbus intercept
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -88,7 +88,7 @@ end component;
component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -112,7 +112,7 @@ component sn_humanio_emu_rbus is -- sn_humanio rbus emulator
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -130,7 +130,7 @@ component rgbdrv_analog_rbus is -- rgb analog from rbus
generic (
DWIDTH : positive := 8; -- dimmer width
ACTLOW : slbit := '0'; -- invert output polarity
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
RB_ADDR : slv16 := x"0000");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

4
rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: rgbdrv_analog_rbus.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: rgbdrv_analog_rbus.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2016-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -50,7 +50,7 @@ entity rgbdrv_analog_rbus is -- rgb analog from rbus
generic (
DWIDTH : positive := 8; -- dimmer width
ACTLOW : slbit := '0'; -- invert output polarity
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
RB_ADDR : slv16 := x"0000");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

8
rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd
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@@ -1,6 +1,6 @@
-- $Id: sn_humanio_demu_rbus.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sn_humanio_demu_rbus.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.0.29-0.31
-- Tool versions: xst 13.3-14.7; ghdl 0.0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -69,7 +69,7 @@ use work.bpgenlib.all;
entity sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

8
rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sn_humanio_emu_rbus.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sn_humanio_emu_rbus.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2017-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2017.1; ghdl 0.34
-- Tool versions: viv 2017.1-2019,1; ghdl 0.34-0.35
--
-- Revision History:
-- Date Rev Version Comment
@@ -67,7 +67,7 @@ entity sn_humanio_emu_rbus is -- sn_humanio rbus emulator
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

8
rtl/bplib/bpgen/sn_humanio_rbus.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sn_humanio_rbus.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sn_humanio_rbus.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2010-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4-2017.1; ghdl 0.26-0.34
-- Tool versions: ise 11.4-14.7; viv 2014.4-2019.1; ghdl 0.26-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -98,7 +98,7 @@ entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

1
rtl/bplib/fx2rlink/fx2rlinklib.vbom
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@@ -1,6 +1,7 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rbus/rbdlib.vhd
../../vlib/rlink/rlinklib.vhd
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd

10
rtl/bplib/fx2rlink/fx2rlinklib.vhd
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@@ -1,6 +1,6 @@
-- $Id: fx2rlinklib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: fx2rlinklib.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,10 +16,11 @@
-- Description: Definitions for rlink + fx2 interface combos
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.2.1 use rbaddr_ constants
-- 2015-04-11 666 1.2 rlink_sp1c_fx2: drop ENAESC
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-04-20 509 1.0 Initial version
@@ -31,6 +32,7 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
@@ -56,7 +58,7 @@ component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable

9
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd
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@@ -1,6 +1,6 @@
-- $Id: rlink_sp1c_fx2.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: rlink_sp1c_fx2.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -25,7 +25,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
-- Tool versions: xst 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
@@ -34,6 +34,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.3.1 use rbaddr_ constants
-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
@@ -66,7 +67,7 @@ entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable

10
rtl/bplib/sysmon/sysmon_rbus_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sysmon_rbus_core.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sysmon_rbus_core.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic (all with SYSMON or XADC)
-- Tool versions: viv 2015.4-2016.1; ghdl 0.33
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
@@ -69,8 +69,8 @@ entity sysmon_rbus_core is -- SYSMON interface to rbus
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

14
rtl/bplib/sysmon/sysmonrbuslib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sysmonrbuslib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sysmonrbuslib.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,7 +16,7 @@
-- Description: generic (all with SYSMON or XADC)
--
-- Dependencies: -
-- Tool versions: viv2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-28 770 1.0.1 ensure to_unsigned() has a type natural argument
@@ -117,8 +117,8 @@ component sysmon_rbus_core is -- SYSMON interface to rbus
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -152,7 +152,7 @@ component sysmonx_rbus_base is -- XADC interface to rbus (basic monitor
INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -175,7 +175,7 @@ component sysmonx_rbus_arty is -- XADC interface to rbus (arty pwrmon)
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

8
rtl/bplib/sysmon/sysmonx_rbus_arty.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sysmonx_rbus_arty.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sysmonx_rbus_arty.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: 7series
-- Tool versions: viv 2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
@@ -65,7 +65,7 @@ entity sysmonx_rbus_arty is -- XADC interface to rbus (for arty)
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

8
rtl/bplib/sysmon/sysmonx_rbus_base.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sysmonx_rbus_base.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sysmonx_rbus_base.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: 7series
-- Tool versions: viv 2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
@@ -58,7 +58,7 @@ entity sysmonx_rbus_base is -- XADC interface to rbus (basic monitor
INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

6
rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: rbd_tst_rlink.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: rbd_tst_rlink.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -83,8 +83,8 @@ architecture syn of rbd_tst_rlink is
signal TIM1_DONE : slbit := '0';
signal TIM1_BUSY : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/8: 1111 1111 1110 1xxx
constant rbaddr_tester : slv16 := x"ffe0"; -- ffe0/8: 1111 1111 1110 0xxx
-- rbaddr_rbmon -- default addr - ffe8/8: 1111 1111 1110 1xxx
-- rbaddr_tester -- default addr - ffe0/8: 1111 1111 1110 0xxx
constant rbaddr_eyemon : slv16 := x"ffd0"; -- ffd0/4: 1111 1111 1101 00xx
constant rbaddr_tim1 : slv16 := x"fe11"; -- fe11/1: 1111 1110 0001 0001
constant rbaddr_tim0 : slv16 := x"fe10"; -- fe10/1: 1111 1110 0001 0000

1
rtl/vlib/rbus/rbd_rbmon.vbom
View File

@@ -2,6 +2,7 @@
../slvtypes.vhd
../memlib/memlib.vhd
rblib.vhd
rbdlib.vhd
# components
[sim]../memlib/ram_1swsr_wfirst_gen.vbom
[xst]../memlib/ram_1swsr_wfirst_gen_unisim.vbom

8
rtl/vlib/rbus/rbd_rbmon.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: rbd_rbmon.vhd 1116 2019-03-03 08:24:07Z mueller $
-- $Id: rbd_rbmon.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2010-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,6 +32,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 6.0.2 use rbaddr_ constants
-- 2019-03-02 1116 6.0.1 more robust ack,err trace when busy
-- 2017-04-16 879 6.0 revised interface, add suspend and repeat collapse
-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue
@@ -91,6 +92,7 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.rbdlib.all;
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
-- to control the instantiation. ghdl checks even for not instantiated
@@ -98,8 +100,8 @@ use work.rblib.all;
entity rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#ffe8#,16));
AWIDTH : natural := 9);
RB_ADDR : slv16 := rbaddr_rbmon;
AWIDTH : natural := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset

1
rtl/vlib/rbus/rbd_tester.vbom
View File

@@ -2,6 +2,7 @@
../slvtypes.vhd
../memlib/memlib.vhd
rblib.vhd
rbdlib.vhd
# components
../memlib/fifo_simple_dram.vbom
# design

8
rtl/vlib/rbus/rbd_tester.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: rbd_tester.vhd 1109 2019-02-09 13:36:41Z mueller $
-- $Id: rbd_tester.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2010-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- Test bench: rlink/tb/tb_rlink (used as test target)
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2017.2; ghdl 0.29-0.35
-- Tool versions: xst 12.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
-- 2019-02-09 1109 4.2 use fifo_simple_dram (instead of _1c_dram_raw)
-- 2014-09-05 591 4.1 use new iface with 8 regs
-- 2014-08-30 589 4.0 use new rlink v4 iface and 4 bit STAT
@@ -63,11 +64,12 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.rbdlib.all;
entity rbd_tester is -- rbus dev: rbus tester
-- complete rrirp_aif interface
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#ffe0#,16)));
RB_ADDR : slv16 := rbaddr_tester);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset

9
rtl/vlib/rlink/rlink_sp1c.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rlink_sp1c.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: rlink_sp1c.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,7 +23,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
-- Tool versions: ise 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
@@ -32,6 +32,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
-- 2015-05-02 672 4.2 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL, rearrange XON handling
-- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT
@@ -61,7 +62,7 @@ entity rlink_sp1c is -- rlink_core8+serport_1clock combo
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable

9
rtl/vlib/rlink/rlink_sp2c.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rlink_sp2c.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: rlink_sp2c.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,10 +23,11 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2016-03-28 755 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
@@ -53,7 +54,7 @@ entity rlink_sp2c is -- rlink_core8+serport_2clock2 combo
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- U|clock (user design)
CE_USEC : in slbit; -- U|1 usec clock enable

1
rtl/vlib/rlink/rlinklib.vbom
View File

@@ -1,5 +1,6 @@
# libs
../slvtypes.vhd
../rbus/rblib.vhd
../rbus/rbdlib.vhd
../serport/serportlib.vbom
rlinklib.vhd

12
rtl/vlib/rlink/rlinklib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rlinklib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: rlinklib.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,11 +16,12 @@
-- Description: Definitions for rlink interface and bus entities
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
--
-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
-- 2016-03-28 755 4.2 add rlink_sp2c
-- 2015-04-11 666 4.1.2 rlink_core8: add ESC(XON|FILL);
-- rlink_sp1c: rename ENAESC->ESCFILL
@@ -65,6 +66,7 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.serportlib.all;
package rlinklib is
@@ -232,7 +234,7 @@ component rlink_sp1c is -- rlink_core8+serport_1clock combo
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
@@ -267,7 +269,7 @@ component rlink_sp2c is -- rlink_core8+serport_2clock2 combo
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- U|clock (user design)
CE_USEC : in slbit; -- U|1 usec clock enable

9
rtl/vlib/rlink/tb/tb_rlink.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_rlink.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: tb_rlink.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -26,10 +26,11 @@
-- rlink_serport (via tbd_rlink_serport)
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
-- Tool versions: xst 8.2-14.7; viv 2019.1; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 4.1.2 use rbaddr_ constants
-- 2016-09-10 806 4.1.1 use clkdivce_tb
-- 2014-10-12 596 4.1 use readgen_ea; add get_cmd_ea; labo instead of stat
-- add txblk,rxblk,rxrbeg,rxrend,rxcbs,anmsg commands
@@ -266,7 +267,7 @@ begin
RBTEST : rbd_tester
generic map (
RB_ADDR => slv(to_unsigned(16#ffe0#,16)))
RB_ADDR => rbaddr_tester)
port map (
CLK => CLK,
RESET => '0',

17
rtl/vlib/rlink/tb/tbd_tba_ttcombo.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tbd_tba_ttcombo.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: tbd_tba_ttcombo.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -29,10 +29,11 @@
-- 2010-12-29 351 12.1 M53d xc3s1000-4 192 538 32 342 s 10.1
-- 2010-12-23 347 12.1 M53d xc3s1000-4 78 204 32 133 s 8.1
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 4.0.1 use rbaddr_ constants
-- 2014-09-13 593 4.0 use new rlink v4 iface and 4 bit STAT; new addr
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-11-22 432 3.1.2 now numeric_std clean
@@ -46,8 +47,8 @@
--
-- address layout:
--
-- rbd_rbmon ffe8/8
-- rbd_tester ffe0/8
-- rbd_rbmon ffe8/8 -- default
-- rbd_tester ffe0/8 -- default
-- rbd_bram fe00/2
--
@@ -105,7 +106,7 @@ begin
TEST: rbd_tester
generic map (
RB_ADDR => slv(to_unsigned(16#ffe0#,16)))
RB_ADDR => rbaddr_tester)
port map (
CLK => CLK,
RESET => RESET,
@@ -117,7 +118,7 @@ begin
MON: rbd_rbmon
generic map (
RB_ADDR => slv(to_unsigned(16#ffe8#,16)),
RB_ADDR => rbaddr_rbmon,
AWIDTH => 9)
port map (
CLK => CLK,
@@ -129,7 +130,7 @@ begin
BRAM: rbd_bram
generic map (
RB_ADDR => slv(to_unsigned(16#fe00#,16)))
RB_ADDR => x"fe00")
port map (
CLK => CLK,
RESET => RESET,

31
rtl/w11a/pdp11.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11.vhd 1116 2019-03-03 08:24:07Z mueller $
-- $Id: pdp11.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,10 +16,11 @@
-- Description: Definitions for pdp11 components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2016.2-2018.3; ghdl 0.18-0.35
-- Tool versions: ise 8.2-14.7; viv 2016.2-2019.1; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.6.12 add rbaddr_ constants
-- 2019-03-01 1116 1.6.11 define c_init_rbf_greset
-- 2018-10-07 1054 1.6.10 add DM_STAT_EXP; add DM_STAT_SE.itimer
-- 2018-10-05 1053 1.6.9 drop DM_STAT_SY; add DM_STAT_CA, use in pdp11_cache
@@ -113,6 +114,14 @@ use work.rblib.all;
package pdp11 is
-- default rbus base addresses and offsets
constant rbaddr_cpu0_core : slv16 := x"0000"; -- cpu0 core base
constant rbaddr_cpu0_ibus : slv16 := x"4000"; -- cpu0 ibus window base
constant rbaddr_dmscnt_off : slv16 := x"0040"; -- dmscnt offset
constant rbaddr_dmcmon_off : slv16 := x"0048"; -- dmcmon offset
constant rbaddr_dmhbpt_off : slv16 := x"0050"; -- dmhbpt offset
constant rbaddr_dmpcnt_off : slv16 := x"0060"; -- dmpcnt offset
type psw_type is record -- processor status
cmode : slv2; -- current mode
pmode : slv2; -- previous mode
@@ -1259,8 +1268,8 @@ end component;
component pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv16 := slv(to_unsigned(16#0000#,16));
RB_ADDR_IBUS : slv16 := slv(to_unsigned(16#4000#,16)));
RB_ADDR_CORE : slv16 := rbaddr_cpu0_core;
RB_ADDR_IBUS : slv16 := rbaddr_cpu0_ibus);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -1327,7 +1336,7 @@ end component;
component pdp11_dmscnt is -- debug&moni: state counter
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0040#,16)));
RB_ADDR : slv16 := rbaddr_dmscnt_off);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -1341,7 +1350,7 @@ end component;
component pdp11_dmcmon is -- debug&moni: cpu monitor
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0048#,16));
RB_ADDR : slv16 := rbaddr_dmcmon_off;
AWIDTH : natural := 8;
SNUM : boolean := false);
port (
@@ -1358,7 +1367,7 @@ end component;
component pdp11_dmhbpt is -- debug&moni: hardware breakpoint
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0050#,16));
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
NUNIT : natural := 2);
port (
CLK : in slbit; -- clock
@@ -1375,7 +1384,7 @@ end component;
component pdp11_dmhbpt_unit is -- dmhbpt - indivitial unit
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0050#,16));
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
INDEX : natural := 0);
port (
CLK : in slbit; -- clock
@@ -1392,9 +1401,9 @@ end component;
component pdp11_dmpcnt is -- debug&moni: performance counters
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0060#,16)); -- rbus address
VERS : slv8 := slv(to_unsigned(0, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
RB_ADDR : slv16 := rbaddr_dmpcnt_off; -- rbus address
VERS : slv8 := slv(to_unsigned(0, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset

9
rtl/w11a/pdp11_core_rbus.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_core_rbus.vhd 1116 2019-03-03 08:24:07Z mueller $
-- $Id: pdp11_core_rbus.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,7 +19,7 @@
-- Test bench: tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.5.4 use rbaddr_ constants
-- 2019-03-02 1116 1.5.3 rename state field rbinit to greset
-- 2016-05-22 767 1.5.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-07-10 700 1.5.1 add cpuact logic, redefine lam as cpuact 1->0
@@ -108,8 +109,8 @@ use work.pdp11.all;
entity pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv16 := slv(to_unsigned(16#0000#,16));
RB_ADDR_IBUS : slv16 := slv(to_unsigned(16#4000#,16)));
RB_ADDR_CORE : slv16 := rbaddr_cpu0_core;
RB_ADDR_IBUS : slv16 := rbaddr_cpu0_ibus);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset

9
rtl/w11a/pdp11_dmcmon.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_dmcmon.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_dmcmon.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2017.1; ghdl 0.31-0.34
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 2.0.1 use rbaddr_ constants
-- 2017-04-22 884 2.0 use DM_STAT_SE.idle; revised interface, add suspend
-- 2015-08-03 709 1.0 Initial version
-- 2015-07-05 697 0.1 First draft
@@ -140,7 +141,7 @@ use work.pdp11.all;
entity pdp11_dmcmon is -- debug&moni: cpu monitor
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0048#,16));
RB_ADDR : slv16 := rbaddr_dmcmon_off;
AWIDTH : natural := 8;
SNUM : boolean := false);
port (

9
rtl/w11a/pdp11_dmhbpt.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_dmhbpt.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_dmhbpt.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2015-07-19 702 1.0 Initial version
-- 2015-07-05 698 0.1 First draft
------------------------------------------------------------------------------
@@ -44,7 +45,7 @@ use work.pdp11.all;
entity pdp11_dmhbpt is -- debug&moni: hardware breakpoint
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0050#,16));
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
NUNIT : natural := 2);
port (
CLK : in slbit; -- clock

9
rtl/w11a/pdp11_dmhbpt_unit.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_dmhbpt_unit.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_dmhbpt_unit.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,7 +19,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2015-07-19 702 1.0 Initial version
-- 2015-07-05 698 0.1 First draft
------------------------------------------------------------------------------
@@ -59,7 +60,7 @@ use work.pdp11.all;
entity pdp11_dmhbpt_unit is -- dmhbpt - indivitial unit
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0050#,16));
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
INDEX : natural := 0);
port (
CLK : in slbit; -- clock

1
rtl/w11a/pdp11_dmpcnt.vbom
View File

@@ -2,6 +2,7 @@
../vlib/slvtypes.vhd
../vlib/memlib/memlib.vhd
../vlib/rbus/rblib.vhd
pdp11.vbom
# components
[sim]../vlib/memlib/ram_1swar_gen.vbom
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom

14
rtl/w11a/pdp11_dmpcnt.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_dmpcnt.vhd 1051 2018-09-29 15:29:11Z mueller $
-- $Id: pdp11_dmpcnt.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,7 +19,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2-2018.2; ghdl 0.34
-- Tool versions: ise 14.7; viv 2017.2-2019.1; ghdl 0.34-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2018-09-29 1051 1.0 Initial version
-- 2018-09-23 1050 0.1 First draft
------------------------------------------------------------------------------
@@ -102,12 +103,13 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.pdp11.all;
entity pdp11_dmpcnt is -- debug&moni: performance counters
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0060#,16)); -- rbus address
VERS : slv8 := slv(to_unsigned(1, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
RB_ADDR : slv16 := rbaddr_dmpcnt_off; -- rbus address
VERS : slv8 := slv(to_unsigned(1, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset

9
rtl/w11a/pdp11_dmscnt.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_dmscnt.vhd 1050 2018-09-23 15:46:42Z mueller $
-- $Id: pdp11_dmscnt.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,7 +19,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.1.2 use rbaddr_ constants
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-28 721 1.1 use laddr/waddr; use ena instead of cnt;
-- 2015-07-19 702 1.0 Initial version
@@ -59,7 +60,7 @@ use work.pdp11.all;
entity pdp11_dmscnt is -- debug&moni: state counter
generic (
RB_ADDR : slv16 := slv(to_unsigned(16#0040#,16)));
RB_ADDR : slv16 := rbaddr_dmscnt_off);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset

13
rtl/w11a/pdp11_sys70.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_sys70.vhd 1116 2019-03-03 08:24:07Z mueller $
-- $Id: pdp11_sys70.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,10 +32,11 @@
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2018.3; ghdl 0.33-0.35
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.3.3 use rbaddr_ constants
-- 2019-03-02 1116 1.3.2 add RESET_SYS; fix pdp11_mem70 reset
-- 2019-02-16 1112 1.3.1 add ibd_ibtst
-- 2018-10-13 1055 1.3 drop ITIMER,DM_STAT_DP out ports, use DM_STAT_EXP
@@ -269,7 +270,7 @@ begin
begin
I0: pdp11_dmscnt
generic map (
RB_ADDR => slv(to_unsigned(16#0040#,16)))
RB_ADDR => rbaddr_dmscnt_off)
port map (
CLK => CLK,
RESET => RESET_SYS,
@@ -285,7 +286,7 @@ begin
begin
I0: pdp11_dmcmon
generic map (
RB_ADDR => slv(to_unsigned(16#0048#,16)),
RB_ADDR => rbaddr_dmcmon_off,
AWIDTH => sys_conf_dmcmon_awidth,
SNUM => sys_conf_dmscnt)
port map (
@@ -304,7 +305,7 @@ begin
begin
I0: pdp11_dmhbpt
generic map (
RB_ADDR => slv(to_unsigned(16#0050#,16)),
RB_ADDR => rbaddr_dmhbpt_off,
NUNIT => sys_conf_dmhbpt_nunit)
port map (
CLK => CLK,
@@ -399,7 +400,7 @@ begin
I0: pdp11_dmpcnt
generic map (
RB_ADDR => slv(to_unsigned(16#0060#,16)), -- rbus address
RB_ADDR => rbaddr_dmpcnt_off, -- rbus address
VERS => slv(to_unsigned(1, 8)), -- counter layout version
-- 33222222222211111111110000000000
-- 10987654321098765432109876543210

11
rtl/w11a/tb/tbd_tba_pdp11core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tbd_tba_pdp11core.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: tbd_tba_pdp11core.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -29,9 +29,10 @@
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.34
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.6.2 use rbaddr_ constants
-- 2018-10-07 1054 1.6.1 drop ITIMER from core
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
@@ -141,8 +142,8 @@ begin
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => slv(to_unsigned(16#0000#,16)),
RB_ADDR_IBUS => slv(to_unsigned(16#4000#,16)))
RB_ADDR_CORE => rbaddr_cpu0_core,
RB_ADDR_IBUS => rbaddr_cpu0_ibus)
port map (
CLK => CLK,
RESET => RESET,