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use DM_STAT_EXP for signals exported by pdp11_sys70

Browse Source 
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
This commit is contained in:
wfjm
2018-10-13 15:18:59 +02:00
parent a500e62912
commit c7e606d9b0
22 changed files with 620 additions and 495 deletions
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25
rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vhd
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@@ -1,6 +1,6 @@
-- $Id: pdp11_hio70_arty.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_hio70_arty.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,10 +18,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.31
-- Tool versions: viv 2015.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2016-02-27 737 1.0 Initial version
------------------------------------------------------------------------------
--
@@ -75,7 +76,7 @@ entity pdp11_hio70_arty is -- hio led+rgb for sys70 for arty
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
IOLEDS : in slv4; -- serport ioleds
ABCLKDIV : in slv16; -- serport clock divider
@@ -108,9 +109,9 @@ begin
idat16 := (others=>'0');
case MODE(1 downto 0) is
when "00" => idat16 := ABCLKDIV;
when "01" => idat16 := DM_STAT_DP.pc;
when "01" => idat16 := DM_STAT_EXP.dp_pc;
when "10" => idat16 := DISPREG;
when "11" => idat16 := DM_STAT_DP.dsrc;
when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
@@ -131,10 +132,10 @@ begin
if MODE(0) = '1' then
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '0' then
if unsigned(DM_STAT_DP.psw.pri) = 0 then
if unsigned(DM_STAT_EXP.dp_psw.pri) = 0 then
irgb_g(2) := '1';
else
irgb_g(3) := '1';
@@ -159,10 +160,10 @@ begin
end if;
else -- LED+RGB show DR emulation
iled := DM_STAT_DP.dsrc(15 downto 12);
irgb_b := DM_STAT_DP.dsrc(11 downto 8);
irgb_g := DM_STAT_DP.dsrc( 7 downto 4);
irgb_r := DM_STAT_DP.dsrc( 3 downto 0);
iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
irgb_b := DM_STAT_EXP.dp_dsrc(11 downto 8);
irgb_g := DM_STAT_EXP.dp_dsrc( 7 downto 4);
irgb_r := DM_STAT_EXP.dp_dsrc( 3 downto 0);
end if; -- MODE(2) = '0'
else -- LED+RGB show one of four regs

94
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_arty.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_br_arty.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -53,6 +53,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.3 use DM_STAT_EXP
-- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 1.2 use serport_2clock2
-- 2016-03-19 748 1.1.2 define rlink SYSID
@@ -171,13 +172,13 @@ architecture syn of sys_w11a_br_arty is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -313,33 +314,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@@ -350,7 +360,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -391,19 +401,19 @@ begin
HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled

19
rtl/sys_gen/w11a/artys7_bram/pdp11_hio70_artys7.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_hio70_artys7.vhd 1038 2018-08-11 12:39:52Z mueller $
-- $Id: pdp11_hio70_artys7.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,6 +22,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2018-08-05 1038 1.0 Initial version (cloned from pdp11_hio70_artya7)
------------------------------------------------------------------------------
--
@@ -71,7 +72,7 @@ entity pdp11_hio70_artys7 is -- hio led+rgb for sys70 for artys7
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
IOLEDS : in slv4; -- serport ioleds
ABCLKDIV : in slv16; -- serport clock divider
@@ -104,9 +105,9 @@ begin
idat16 := (others=>'0');
case MODE(1 downto 0) is
when "00" => idat16 := ABCLKDIV;
when "01" => idat16 := DM_STAT_DP.pc;
when "01" => idat16 := DM_STAT_EXP.dp_pc;
when "10" => idat16 := DISPREG;
when "11" => idat16 := DM_STAT_DP.dsrc;
when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
@@ -127,7 +128,7 @@ begin
if MODE(0) = '1' then
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '0' then
irgb_g(1) := '1';
@@ -149,10 +150,10 @@ begin
end if;
else -- LED+RGB show DR emulation
iled := DM_STAT_DP.dsrc(15 downto 12);
irgb_b := DM_STAT_DP.dsrc( 9 downto 8);
irgb_g := DM_STAT_DP.dsrc( 5 downto 4);
irgb_r := DM_STAT_DP.dsrc( 1 downto 0);
iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
irgb_b := DM_STAT_EXP.dp_dsrc( 9 downto 8);
irgb_g := DM_STAT_EXP.dp_dsrc( 5 downto 4);
irgb_r := DM_STAT_EXP.dp_dsrc( 1 downto 0);
end if; -- MODE(2) = '0'
else -- LED+RGB show one of four regs

94
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_as7.vhd 1047 2018-09-16 11:08:41Z mueller $
-- $Id: sys_w11a_br_as7.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -45,6 +45,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP
-- 2018-08-11 1038 1.0 Initial version (derived from sys_w11a_aa7)
------------------------------------------------------------------------------
--
@@ -150,13 +151,13 @@ architecture syn of sys_w11a_br_as7 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -292,33 +293,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@@ -329,7 +339,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -370,19 +380,19 @@ begin
HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled

88
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_b3.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_b3.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -50,6 +50,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.4 use DM_STAT_EXP
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.2 define rlink SYSID
@@ -170,13 +171,13 @@ architecture syn of sys_w11a_b3 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -311,33 +312,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@@ -348,7 +358,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -392,16 +402,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------

90
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_c7.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_c7.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -34,7 +34,7 @@
-- Test bench: tb/tb_sys_w11a_c7
--
-- Target Devices: generic
-- Tool versions: viv 2018.2; ghdl 0.34
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
@@ -45,6 +45,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.2 use DM_STAT_EXP
-- 2017-06-27 918 1.1.1 use 16 kB cache (all BRAM's used up)
-- 2017-06-25 916 1.1 add bram_memctl for 672 kB total memory
-- 2017-06-24 914 1.0 Initial version (derived from sys_w11a_n4)
@@ -123,13 +124,13 @@ architecture syn of sys_w11a_c7 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -283,33 +284,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@@ -320,7 +330,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -430,16 +440,16 @@ begin
LWIDTH => ELED'length,
DCWIDTH => 3)
port map (
SEL_LED => ESWI(3),
SEL_DSP => ESWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => ELED,
DSP_DAT => EDSP_DAT
SEL_LED => ESWI(3),
SEL_DSP => ESWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => ELED,
DSP_DAT => EDSP_DAT
);
EHIO : sn_humanio_emu_rbus -- emulated hio ----------------------

88
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n2.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_n2.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2010-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -71,6 +71,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.3 use DM_STAT_EXP
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
@@ -274,14 +275,14 @@ architecture syn of sys_w11a_n2 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -399,33 +400,42 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@@ -435,7 +445,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -500,16 +510,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
);
proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------

88
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n3.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_n3.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2011-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -56,6 +56,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.3 use DM_STAT_EXP
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
@@ -234,14 +235,14 @@ architecture syn of sys_w11a_n3 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -371,33 +372,42 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@@ -407,7 +417,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -473,16 +483,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
);
proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------

88
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n4.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_n4.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -53,6 +53,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.4 use DM_STAT_EXP
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.1 define rlink SYSID
@@ -199,14 +200,14 @@ architecture syn of sys_w11a_n4 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -347,33 +348,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@@ -383,7 +393,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -440,16 +450,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------

88
rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_n4d.vhd 1047 2018-09-16 11:08:41Z mueller $
-- $Id: sys_w11a_br_n4d.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -42,6 +42,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP
-- 2017-01-04 838 1.0 Initial version (derived from sys_w11a_br_n4)
------------------------------------------------------------------------------
--
@@ -167,14 +168,14 @@ architecture syn of sys_w11a_br_n4d is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -307,33 +308,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@@ -343,7 +353,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -387,16 +397,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------

88
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_s3.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_s3.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2007-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -77,6 +77,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.2 use DM_STAT_EXP
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form
@@ -251,14 +252,14 @@ architecture syn of sys_w11a_s3 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@@ -349,33 +350,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@@ -385,7 +395,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@@ -431,16 +441,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------