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- interim release w11a_V0.56 (untagged)

Browse Source 
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
        in the file README_USB-VID-PID.txt. You'll be responsible for any
        misuse of the defaults provided with the project sources !!
This commit is contained in:
Walter F.J. Mueller
2013-01-02 21:06:53 +00:00
parent f6775f7d05
commit cbd8ce3468
218 changed files with 17409 additions and 963 deletions
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26
Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -6,13 +6,19 @@
#
# Revision History:
# Date Rev Version Comment
# 2012-12-29 466 1.0.5 add tst_rlink_cuff
# 2011-12-26 445 1.0.4 add tst_fx2loop
# 2011-12-23 444 1.0.3 enforce -j 1 in sub-makes
# 2011-11-27 433 1.0.2 add new nexys3 ports
# 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio
# 2011-07-09 391 1.0 Initial version
#
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic3
SYN_all += rtl/sys_gen/tst_rlink/nexys2
SYN_all += rtl/sys_gen/tst_rlink/nexys3
SYN_all += rtl/sys_gen/tst_rlink/s3board
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
SYN_all += rtl/sys_gen/tst_serloop/nexys2
SYN_all += rtl/sys_gen/tst_serloop/nexys3
SYN_all += rtl/sys_gen/tst_serloop/s3board
@@ -43,8 +49,8 @@ SIM_all += rtl/w11a/tb
#
all :
@echo "no default action defined, use"
@echo " make all_sim"
@echo " make all_syn"
@echo " make -j 4 all_sim"
@echo " make -j 4 all_syn"
@echo " make clean"
@echo " make clean_sim"
@echo " make clean_syn"
@@ -58,10 +64,20 @@ clean_syn :
for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done
#
all_sim : $(SIM_all)
#
all_syn : $(SYN_all)
@if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \
echo "++++++++++ some designs have no timing closure: ++++++++++"; \
find -name "*_par.log" | xargs grep -L 'All constraints were met'; \
echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
fi
#
# Neither ghdl nor xst allow multiple parallel compiles in one directory.
# The following ensures that the sub-makes are called with -j 1 and will
# not try to run multiple compiles on one directory.
#
$(SIM_all):
$(MAKE) -C $@
$(MAKE) -j 1 -C $@
$(SYN_all):
$(MAKE) -C $@
$(MAKE) -j 1 -C $@
#

181
doc/INSTALL.txt
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@@ -1,23 +1,27 @@
# $Id: INSTALL.txt 433 2011-11-27 22:04:39Z mueller $
# $Id: INSTALL.txt 467 2013-01-02 19:49:05Z mueller $
Guide to install and build w11a systems, test benches and support software
Table of content:
1. Download
2. Setup environment variables
3. Compile UNISIM/SIMPRIM libraries for ghdl
4. Compile and install the support software
2. System requirements
3. Setup system environment
a. Setup environment variables
b. Setup USB access
4. Compile UNISIM/SIMPRIM libraries for ghdl
5. Compile and install the support software
a. Compile sharable libraries
b. Setup Tcl packages
5. The build system
6. Building test benches
c. Rebuild Cypress FX2 firmware
6. The build system
7. Building test benches
a. General instructions
b. Available test benches
7. Building systems
8. Building systems
a. General instructions
b. Available systems
b. Configuring FPGAs
c. Available systems
1. Download ---------------------------------------------------------------
@@ -34,7 +38,50 @@ Guide to install and build w11a systems, test benches and support software
cd <wdir>
svn co http://opencores.org/ocsvn/w11/w11/trunk
2. Setup environment variables --------------------------------------------
2. System requirements ----------------------------------------------------
This project contains not only VHDL code but also support software. Therefore
quite a few software packages are expected to be installed. The following
list gives the Ubuntu/Debian package names, but mapping this to other
distributions should be straight forward.
- building the bit files for the FPGAs requires a Xilinx WebPACK installation
- building and using the RLink backend software requires:
- full C/C++ development chain (gcc,g++,cpp,make)
-> package: build-essential
- Boost C++ library (>= 1.40), with date-time, thread, and regex
-> package: libboost-dev libboost-date-time-dev libboost-thread-dev
libboost-regex-dev
- libusb 1.0 (>= 1.0.6)
-> package: libusb-1.0-0-dev
- Perl (>= 5.10) (usually included in base installations)
- Tcl (>= 8.4), with tclreadline support
-> package: tcl tcl-dev tcllib tclreadline
- the download contains pre-build firmware images for the Cypress FX2
USB Interface. Re-building them requires
- Small Device C Compiler
-> package: sdcc sdcc-ucsim
- for FX2 firmware download and jtag programming over USB one needs
- fxload
-> package: fxload
- urjtag
-> package: urjtag for Ubuntu 12.04
-> see INSTALL_urjtag.txt for other distributions !!
- for VHDL simulations one needs
- ghdl
-> see INSTALL_ghdl.txt for the unfortunately gory details
- optional but very useful is:
- gtkwave
-> package: gtkwave
3. Setup system environment -----------------------------------------------
3a. Setup environment variables --------------------------------------
The make flow for building test benches (ghdl and ISim based) and systems
(Xilinx xst based) as well as the support software (mainly the rlink backend
@@ -43,6 +90,8 @@ Guide to install and build w11a systems, test benches and support software
- the definition of the environment variables:
- RETROBASE: must refer to the installation root directory
- BOOSTINC: pathname for includes of boost library
- TCLINC: pathname for includes of Tcl runtime library
- RETRO_FX2_VID and RETRO_FX2_PID: default USB VID/PID, see below
- that the tools binary directory is in the path
- that the tools library directory is in the library path
@@ -54,14 +103,42 @@ Guide to install and build w11a systems, test benches and support software
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RETROBASE/tools/lib
In most cases the boost library version coming with the distribution will
work, in those cases simply use
work, similar for Tcl, in those cases simply use
export BOOSTINC=/usr/include
export TCLINC=/usr/include/tcl8.5
After that building functional model based test benches will work. If you
want to also build post-xst or post-par test benches read next section.
3. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
If the Cypress USB controller available on Digilent Nexys2, Nexys3 and
Atlys boards is used the default USB VID and PID is defined by two
environment variables. For internal lab use one can use
export RETRO_FX2_VID=16c0
export RETRO_FX2_PID=03ef
!! Carefully read the disclaimer about usage of USB VID/PID numbers !!
!! in the file README_USB-VID-PID.txt. You'll be responsible for any !!
!! misuse of the defaults provided with the project sources. !!
!! Usage of this VID/PID in any commercial product is forbidden. !!
3b. Setup USB access -------------------------------------------------
For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
Atlys boards 'udev' rules must be setup to allow user level access to
these devices. A set of rules is provided under
$RETROBASE/tools/fx2/sys
Follow the 'README.txt' file in this directory.
Notes:
- the provided udev rules use the VID/PID for 'internal lab use' as
described above. If other VID/PID used the file must be modified.
- your user account must be in group 'plugdev' (should be the default).
4. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
The build system for test benches also supports test benches run against
the gate level models derived after the xst, map or par step. In this
@@ -83,17 +160,18 @@ Guide to install and build w11a systems, test benches and support software
If you have several WebPack versions installed, repeat for each version.
4. Compile and install the support software -------------------------------
5. Compile and install the support software -------------------------------
4a. Compile sharable libraries ---------------------------------------
5a. Compile sharable libraries ---------------------------------------
Required tools and libraries:
g++ >= 4.3 (decltype support assumed in usage of boost::bind)
boost >= 1.35 (boost::thread api changed, new one is used)
linusb >= 1.0.5 (timerfd support)
Build was tested under:
ubuntu lucid (10.04 LTS): gcc 4.4.3 boost 1.40.0
debian lenny (5.0.8): gcc 4.3.2 boost 1.xx.x (t.b.c.)
ubuntu lucid (12.04 LTS): gcc 4.6.3 boost 1.46.1 libusb 1.0.9
debian squezze (6.0.6): gcc 4.4.5 boost 1.46.1 libusb 1.0.8
To build all sharable libraries
@@ -106,7 +184,7 @@ Guide to install and build w11a systems, test benches and support software
rm_dep
make realclean
4b. Setup Tcl environment --------------------------------------------
5b. Setup Tcl environment --------------------------------------------
The Tcl files are organized in several packages. To create the Tcl
package files (pkgIndex.tcl)
@@ -131,8 +209,25 @@ Guide to install and build w11a systems, test benches and support software
ln -s $RETROBASE/tools/tcl/.tclshrc .
ln -s $RETROBASE/tools/tcl/.wishrc .
5c. Rebuild Cypress FX2 firmware -------------------------------------
5. The build system -------------------------------------------------------
The download includes pre-build firmware images for the Cypress FX2
USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.
These firmware images are under
$RETROBASE/tools/fx2/bin
To re-build them, e.g. because a different USB VID/PID is to be used
cd $RETROBASE/tools/fx2/src
make clean
make
make install
Please read README_USB_VID-PID.txt carefully to understand the usage
of USB VID and PID.
6. The build system -------------------------------------------------------
Simulation and synthesis tools usually need a list of the VHDL source
files, often in proper compilation order (libraries before components).
@@ -160,9 +255,9 @@ Guide to install and build w11a systems, test benches and support software
even more. Using the vbom's a large number of designs can be easily
maintained.
6. Building test benches --------------------------------------------------
7. Building test benches --------------------------------------------------
6a. General instructions ---------------------------------------------
7a. General instructions ---------------------------------------------
To compile a test bench named <tbench> all is needed is
@@ -182,13 +277,13 @@ Guide to install and build w11a systems, test benches and support software
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
6b. Available test benches -------------------------------------------
7b. Available test benches -------------------------------------------
See file w11a_tb_guide.txt
7. Building systems -------------------------------------------------------
8. Building systems -------------------------------------------------------
7a. General instructions ---------------------------------------------
8a. General instructions ---------------------------------------------
To generate a bit file for a system named <sys> all is needed is
@@ -214,7 +309,37 @@ Guide to install and build w11a systems, test benches and support software
make <sys>.ngc
make <sys>.ncd
7b. Available systems ------------------------------------------------
A simple 'message filter' system is also integrated into the make build flow.
For many (though not all) systems a .mfset file has been provided which
defines the xst,par and bitgen messages which are considered ok. To see
only the remaining message extracted from the vaious .log files simply
use the make target
make <sys>.mfsum
after a re-build.
8b. Configuring FPGAs ------------------------------------------------
The make flow supports also loading the bitstream into FPGAs, either
via Xilinx Impact, or via the Cypress FX2 USB controller is available.
For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
simply use
make <sys>.iconfig
For using the Cypress FX2 USB controlle on Digilent Nexys2, Nexys3 and
Atlys boards just connect the USB cable and
make <sys>.jconfig
This will automatically check and optionaly re-load the FX2 firmware
to a version matching the FPGA design, generate a .svf file from the
.bit file, and configure the FPGA. In case the bit file is out-of-date
the whole design will be re-implemented before.
8c. Available systems ------------------------------------------------
Note: Currently ready to build versions exist for
Digilent S3BOARD (-1000 FPGA version)
@@ -232,7 +357,13 @@ Guide to install and build w11a systems, test benches and support software
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3
make sys_tst_rlink_n3.bit
2. w11a systems
2. rlink over USB tester
a. for Digilent Nexys2 board
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic
make sys_tst_rlink_cuff_ic_n2.bit
3. w11a systems
a. for Digilent S3BOARD
cd $RETROBASE/rtl/sys_gen/w11a/s3board

27
doc/INSTALL_ghdl.txt Normal file
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@@ -0,0 +1,27 @@
# $Id: INSTALL_ghdl.txt 467 2013-01-02 19:49:05Z mueller $
The w11 project uses the open source VHDL simulator
ghdl
It used to be part of most distributions. Unfortunately the Debian maintainer
for ghdl refused at some point to integrate ghdl into Debian Etch. Therefore
ghdl is part of Debian Lenny, and again of Debian Squeeze (the current
'stable'). So for an up-to-date Debian simply install the ghdl package.
The glitch at Debian unfortunately lead to the removal of ghdl from Ubuntu,
which is based on Debian. Ubuntu Lucid (10.04) and up to Oneiric (11.10)
included ghdl, the currently maintained versions Precise (12.04 LTS) and
Quantal (12.10) don't.
Thanks to Peter Gavin Ubuntu packages for GHDL are available from his PPA
'Personal Package Archives', see
https://launchpad.net/~pgavin/+archive/ghdl
So to install ghdl under Ubuntu use
sudo add-apt-repository ppa:pgavin/ghdl
sudo apt-get update
sudo apt-get install ghdl

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doc/INSTALL_urjtag.txt Normal file
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@@ -0,0 +1,51 @@
# $Id: INSTALL_urjtag.txt 467 2013-01-02 19:49:05Z mueller $
The w11 project uses the open source JTAG Access software from the
SourceForge project
urjtag
for configuring FPGA over the Cypress FX2 USB Interface available on Digilent
Nexys2, Nexys3 and Atlys boards.
The most recent version works fine. This version is delivered with
Ubuntu 12.04 LTS and later Ubuntu versions. In this case simply install the
package 'urjtag'. Try the command
jtag
it should print
UrJTAG 0.10 #2007
and show a version number of '#2007' or higher.
Old versions unfortunately have a string size limitation problem with can
lead to problems when used with Digilent S3BOARDS (or other cases with
multiple devices in the jtag chain). Therefore for
Debian Squeeze and older
Ubuntu 11.10 (oneiric) and older
or if the 'jtag' command prints something like
UrJTAG 0.10 #1502
UrJTAG 0.9 #1476
it is advisible to install the urjtag software from sources.
Simlest is to install an up-to-date version directly from the SourceForge
svn repository, start at
http://sourceforge.net/scm/?type=svn&group_id=193266&source=navbar
do a 'svn co' for revision 2007 or later, build and install.
Alternatively start with the V0.10 (rev #1502) tarball available from
http://sourceforge.net/projects/urjtag/files/?source=navbar
and download
urjtag-0.10.tar.gz (dated 2009-04-17)
Change in file src/cmd/parse.c the line
#define MAXINPUTLINE 100 /* Maximum input line length */
and replace '100' with '512', build and install.

126
doc/README.txt
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@@ -1,4 +1,4 @@
# $Id: README.txt 442 2011-12-23 10:03:28Z mueller $
# $Id: README.txt 467 2013-01-02 19:49:05Z mueller $
Release notes for w11a
@@ -26,6 +26,7 @@ Release notes for w11a
rtl VHDL sources
rtl/bplib - board and component support libs
rtl/bplib/atlys - for Digilent Atlys board
rtl/bplib/fx2lib - for Cypress FX2 USB interface controller
rtl/bplib/issi - for ISSI parts
rtl/bplib/micron - for Micron parts
rtl/bplib/nexys2 - for Digilent Nexsy2 board
@@ -34,8 +35,12 @@ Release notes for w11a
rtl/bplib/s3board - for Digilent S3BOARD
rtl/ibus - ibus devices (UNIBUS peripherals)
rtl/sys_gen - top level designs
rtl/sys_gen/tst_fx2loop - top level designs for Cypress FX2 tester
nexys2 - systems for Nexsy2
rtl/sys_gen/tst_rlink - top level designs for an rlink tester
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
rtl/sys_gen/tst_rlink_cuff - top level designs for rlink over FX2 tester
nexys2 - systems for Nexsy2
rtl/sys_gen/tst_serloop - top level designs for serport loop tester
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
rtl/sys_gen/tst_snhumanio - top level designs for human I/O tester
@@ -56,16 +61,77 @@ Release notes for w11a
tools/bin - scripts and binaries
tools/dox - Doxygen documentation configuration
tools/make - make includes
tools/src - C++ sources
tools/fx2 - Firmware for Cypress FX2 USB Interface
tools/fx2/bin - pre-build firmware images in .ihx format
tools/fx2/src - C and asm sources
tools/fx2/sys - udev rules for USB on fpga eval boards
tools/src - C++ sources for rlink backend software
tools/src/librlink - basic rlink interface
tools/src/librlinktpp - C++ to tcl binding for rlink interface
tools/src/librtools - general support classes and methods
tools/src/librtcltools - support classes to implement Tcl bindings
tools/src/librtools - general support classes and methods
tools/src/librutiltpp - Tcl support commands implemented in C++
tools/tcl - Tcl scripts
3. Change Log ----------------------------------------------------------------
- trunk (2013-01-02: svn rev 17(oc) 467(wfjm); untagged w11a_V0.56) ++++++++++
- Summary
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
- New refernce system
The development and test system was upgraded from Kubuntu 10.04 to 12.04.
The version of several key tools and libraries changed:
linux kernel 3.2.0 (was 2.6.32)
gcc/g++ 4.6.3 (was 4.4.3)
boost 1.46.1 (was 1.40)
libusb 1.0.9 (was 1.0.6)
perl 5.14.2 (was 5.10.1)
tcl 8.5.11 (was 8.4.19)
xilinx ise 13.3 (was 13.1)
--> see INSTALL.txt, INSTALL_ghdl.txt and INSTALL_urjtag.txt
- New features
- added firmware for Cypress FX2 controller
- tools/fx2
- bin - pre-build firmware images in .ihx file format
- src - C and asm sources
- sys - udev rules for usb interfaces on fpga eval boards
- new modules
- rtl/bplib/fx2lib
- fx2_2fifoctl_ic - Cypress EZ-USB FX2 controller (2 fifo; int clk)
- fx2_3fifoctl_ic - Cypress EZ-USB FX2 controller (3 fifo; int clk)
- new systems
- rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2
- rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2
- rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2
- tools/bin
- xilinx_sdf_ghdl_filter: tool to patch ISE sdf files for usage with ghdl
- Changes
- documentation
- added a 'system requirements' section in INSTALL.txt
- added INSTALL_ghdl.txt and INSTALL_urjtag.txt covering ghdl and urjtag
- added README_USB-VID-PID.txt
- organizational changes
- added TCLINC,RETRO_FX2_VID,RETRO_FX2_PID environment variables
- functional changes
- tools/bin
- vbomconv - file name substitution handling redone; many vboms updated
- retired modules
- vlib/rlink/tb/
- tbcore_rlink_dcm - obsolete, use tbcore_rlink
- trunk (2011-12-23: svn rev 16(oc) 442(wfjm); untagged w11a_V0.55) +++++++++
- Summary
@@ -73,14 +139,6 @@ Release notes for w11a
- added test systems for serport verification
- use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
- Changes
- retired modules
- vlib/rlink
- rlink_rlb2rl - obsolete, now all in rlink_core8
- rlink_base - use now new rlink_core8
- rlink_serport - obsolete, now all in rlink_sp1c
- rlink_base_serport - use now new rlink_sp1c
- New features
- new modules
- vlib/serport
@@ -99,21 +157,29 @@ Release notes for w11a
- sys_gen/tst_serloop/s3board/sys_tst_serloop1_s3
- sys_gen/tst_rlink/s3board/sys_tst_rlink_s3
- Changes
- retired modules
- vlib/rlink
- rlink_rlb2rl - obsolete, now all in rlink_core8
- rlink_base - use now new rlink_core8
- rlink_serport - obsolete, now all in rlink_sp1c
- rlink_base_serport - use now new rlink_sp1c
- trunk (2011-12-04: svn rev 15(oc) 436(wfjm); untagged w11a_V0.54) +++++++++
- Summary
- added support for nexys3 board for w11a
- Changes
- module renames:
bplib/nexys2/n2_cram_dummy -> bplib/nxcramlib/nx_cram_dummy
bplib/nexys2/n2_cram_memctl_as -> bplib/nxcramlib/nx_cram_memctl_as
- New features
- new systems
- sys_gen/w11a/nexys3/sys_w11a_n3
- sys_gen/w11a/nexys3/sys_tst_rlink_n3
- Changes
- module renames:
bplib/nexys2/n2_cram_dummy -> bplib/nxcramlib/nx_cram_dummy
bplib/nexys2/n2_cram_memctl_as -> bplib/nxcramlib/nx_cram_memctl_as
- Bug fixes
- tools/src/lib*: backend libraries compile now on 64 bit systems
@@ -221,6 +287,11 @@ Release notes for w11a
- Introduce rbus protocol V3
- reorganize rbus and rlink modules, many renames
- New features
- vlib/rbus
- added several rbus devices useful for debugging
- rbd_tester: test target, used for example in test benches
- Changes
- module renames:
- the rri (remote-register-interface) components were re-organized and
@@ -282,11 +353,6 @@ Release notes for w11a
- rlink_serport (re-written) is an adapter to a serial interface
- rlink_base_serport (renamed) combines rlink_base and rlink_serport
- New features
- vlib/rbus
- added several rbus devices useful for debugging
- rbd_tester: test target, used for example in test benches
- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) +++++++++++
- Summary
@@ -294,6 +360,15 @@ Release notes for w11a
- Nexys2 systems use DCM
- sys_w11a_n2 now runs with 58 MHz
- New features
- ibus
- added ib_sres_or_mon to check for miss-behaving ibus devices
- added ib_sel to encapsulate address select logic
- nexys2 systems
- now DCM derived system clock supported
- sys_gen/w11a/nexys2
- sys_w11a_n2 now runs with 58 MHz clksys
- Changes
- module renames:
- in future 'box' is used for large autonomous blocks, therefore use
@@ -312,15 +387,6 @@ Release notes for w11a
- basic ibus transaction now takes 2 cycles, one for address select, one
for data exchange. This avoids too long logic paths in the ibus logic.
- New features
- ibus
- added ib_sres_or_mon to check for miss-behaving ibus devices
- added ib_sel to encapsulate address select logic
- nexys2 systems
- now DCM derived system clock supported
- sys_gen/w11a/nexys2
- sys_w11a_n2 now runs with 58 MHz clksys
- Bug fixes
- rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.

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doc/README_USB-VID-PID.txt Normal file
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@@ -0,0 +1,55 @@
# $Id: README_USB-VID-PID.txt 467 2013-01-02 19:49:05Z mueller $
!! Read this disclaimer carefully. You'll be responsible for any !!
!! misuse of the defaults provided with the project sources. !!
USB drivers identify hardware by means of two 16 bit identifiers
VID - Vendor ID
PID - Product ID
In a 'softcoded' USB Controler like the Cypress FX2 each firmware with a
specific functionality should have a unique VID/PID so that drivers can
automatically detect and configure.
The assignment of USB VID/PID is done by usb.org. Unfortunately there is no
VID range reserved for 'development' or 'internal use', the only official way
to obtain a VID is to buy one from usb.org, see
http://www.usb.org/developers/vendor/
The 'usb_jtag' project bought many years ago a small PID range from a re-seller
and used
VID=16C0
PID=06AD
for a project which implemented an Altera UsbBlaster compatible JTAG interface.
The firmware provided with this project provides
- a JTAG interface (via EP1 and EP2)
- data channels (via EP4, EP6 and optionally EP8)
The JTAG part is compatible with the 'usb_jtag' implementation and by extension
compatible with the 'usbblaster' cable driver provided by 'UrJtag', and can
therefore be operated with the 'jtag' command.
However, because the firmware offers additional functionality it should have a
separate VID/PID. Unfortunately it is not longer possible to buy at very modest
cost a PID sub-range, as was done by the 'usb_jtag' project bought many years
ago.
VOTI, a small dutch company, has bought a VID for it's own developments and
made a small range of PID publicly available as "free for internal lab use".
Usage is granted for 'internal lab use only' by VOTI under the conditions:
- the gadgets in which you use those PIDs do not leave your desk
- you won't complain to VOTI if you get in trouble with duplicate PIDs
(for instance because someone else did not follow the previous rule).
- See http://www.voti.nl/pids/pidfaq.html for further details.
The retro11 project uses one of these 'free for internal lab use' PIDs
VID=16C0
PID=03EF
from VOTI as default VID/PID.
==> This is is perfectly fine for plain hobbyist usage
==> But respect the ownership of VOTI of this VID/PID and do not
use this VID/PID for other purposes

24
doc/w11a_tb_guide.txt
View File

@@ -1,4 +1,4 @@
# $Id: w11a_tb_guide.txt 442 2011-12-23 10:03:28Z mueller $
# $Id: w11a_tb_guide.txt 443 2011-12-23 11:21:03Z mueller $
Guide to running w11a test benches
@@ -89,20 +89,22 @@ Guide to running w11a test benches
make tb_rlink_direct
time tbw tb_rlink_direct |\
tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
-> 142355.0 ns 7108: DONE
-> 147755.0 ns 7378: DONE
-> real 0m00.317s user 0m00.324s sys 0m00.028s
- rlink core test via serial port interface
make tb_rlink_serport
time tbw tb_rlink_serport tb_rlink_serport_stim.dat |\
tee tb_rlink_serport_stim2_dsim.log | egrep "(FAIL|DONE)"
-> 72735.0 ns 3627: DONE
-> real 0m00.266s user 0m00.264s sys 0m00.008s
cd $RETROBASE/rtl/vlib/rlink/tb
make tb_rlink_sp1c
time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat |\
tee tb_rlink_sp1c_stim2_dsim.log | egrep "(FAIL|DONE)"
-> 24695.0 ns 1225: DONE
-> real 0m0.133s user 0m0.104s sys 0m0.008s
time tbw tb_rlink_serport tb_rlink_stim.dat |\
tee tb_rlink_serport_dsim.log | egrep "(FAIL|DONE)"
-> 536155.0 ns 26798: DONE
time tbw tb_rlink_sp1c tb_rlink_stim.dat |\
tee tb_rlink_sp1c_dsim.log | egrep "(FAIL|DONE)"
-> 551935.0 ns 27587: DONE
-> real 0m01.714s user 0m01.704s sys 0m00.044s
- w11a core test (using behavioural model)
@@ -125,7 +127,6 @@ Guide to running w11a test benches
- s3board sram controller test
cd $RETROBASE/rtl/bplib/s3board/tb
make tb_s3_sram_memctl
time tbw tb_s3_sram_memctl |\
tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
@@ -136,7 +137,6 @@ Guide to running w11a test benches
- nexys2/nexys3 cram controller test
cd $RETROBASE/rtl/bplib/nxcramlib/tb
make tb_nx_cram_memctl_as
time tbw tb_nx_cram_memctl_as |\
tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"

2
rtl/bplib/bpgen/bp_swibtnled.vbom
View File

@@ -3,7 +3,7 @@
../../vlib/genlib/genlib.vhd
../../vlib/xlib/xlib.vhd
bpgenlib.vbom
## sys_conf : sys_conf.vhd
## ${sys_conf := sys_conf.vhd}
# components
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom

24
rtl/bplib/fx2lib/Makefile Normal file
View File

@@ -0,0 +1,24 @@
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-23 293 1.0 Initial version (cloned..)
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#

13
rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom Normal file
View File

@@ -0,0 +1,13 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
../../vlib/memlib/memlib.vhd
fx2lib.vhd
# components
../../vlib/xlib/iob_reg_o.vbom
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
../../vlib/memlib/fifo_1c_dram.vbom
# design
fx2_2fifoctl_as.vhd

647
rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd Normal file
View File

@@ -0,0 +1,647 @@
-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_as - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; async)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_1c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2
-- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2
-- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2
-- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2
-- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic
-- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed)
-- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's
-- 2011-12-25 445 1.2 change pktend handling, now timer based
-- 2011-11-25 433 1.1.1 now numeric_std clean
-- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle
-- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low
-- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port
-- 2011-07-08 390 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_as;
architecture syn of fx2_2fifoctl_as is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_init, -- s_init: init state
s_rdprep, -- s_rdprep: prepare read
s_rdwait, -- s_rdwait: wait for data
s_rdpwl, -- s_rdpwl: read, strobe low
s_rdpwh, -- s_rdpwh: read, strobe high
s_wrprep, -- s_wrprep: prepare write
s_wrpwl, -- s_wrpwl: write, strobe low
s_wrpwh, -- s_wrpwh: write, strobe high
s_peprep, -- s_peprep: prepare pktend
s_pepwl, -- s_pepwl: pktend, strobe low
s_pepwh -- s_pepwh: pktend, strobe high
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
dlycnt : slv4; -- wait delay counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (rx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_init, -- state
petocnt_init, -- petocnt
'0', -- pepend
(others=>'0'), -- cntdly
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
begin
assert RDPWLDELAY<=2**R_REGS.dlycnt'length and
RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and
WRPWLDELAY<=2**R_REGS.dlycnt'length and
WRPWHDELAY<=2**R_REGS.dlycnt'length and
FLAGDELAY<=2**R_REGS.dlycnt'length
report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)"
severity failure;
assert RXAEMPTY_THRES<=2**RXFAWIDTH and
TXAFULL_THRES<=2**TXFAWIDTH
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => CLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => CLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXSIZE
);
TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => TXSIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_USEC,
FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idly_ld : slbit := '0';
variable idly_val : slv(r.dlycnt'range) := (others=>'0');
variable idly_end : slbit := '0';
variable idly_end1 : slbit := '0';
variable iflag_rdok : slbit := '0';
variable iflag_wrok : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
procedure go_rdprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_rxfifo;
nstate := s_rdprep;
end procedure go_rdprep;
procedure go_wrprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_wrprep;
end procedure go_wrprep;
procedure go_peprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_peprep;
end procedure go_peprep;
procedure go_rdpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islrd : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length));
islrd := '1';
nstate := s_rdpwl;
end procedure go_rdpwl;
procedure go_wrpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islwr : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
islwr := '1';
nstate := s_wrpwl;
end procedure go_wrpwl;
procedure go_pepwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ipktend : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
ipktend := '1';
nstate := s_pepwl;
end procedure go_pepwl;
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
imoni := fx2ctl_moni_init;
iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
idly_ld := '0';
idly_val := (others=>'0');
idly_end := '1';
idly_end1 := '0';
if unsigned(r.dlycnt) /= 0 then
idly_end := '0';
end if;
if unsigned(r.dlycnt) = 1 then
idly_end1 := '1';
end if;
case r.state is
when s_init => -- s_init:
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
when s_rdprep => -- s_rdprep: prepare read
if idly_end = '1' then
n.state := s_rdwait;
end if;
when s_rdwait => -- s_rdwait: wait for data
if r.pepend='1' and TXFIFO_VAL='0' then
go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
elsif iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when s_rdpwl => -- s_rdpwl: read, strobe low
idata_cei := '1';
isloe := '1';
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length));
n.state := s_rdpwh;
else
islrd := '1';
n.state := s_rdpwl;
end if;
-- Note: data is sampled and written into rxfifo in 2nd last cycle in the
-- last cycle the rxfifo busy reflects therefore last written byte
-- and safely indicates whether another byte will fit.
when s_rdpwh => -- s_rdpwh: read, strobe high
idata_cei := '1';
isloe := '1';
if idly_end1 = '1' then -- 2nd last cycle
irxfifo_ena := '1'; -- capture rxdata
end if;
if idly_end = '1' then -- last cycle
if iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
else
n.state := s_rdwait;
end if;
end if;
when s_wrprep => -- s_wrprep: prepare write
if idly_end = '1' then
if iflag_wrok = '1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_wrpwl => -- s_wrpwl: write, strobe low
idata_ceo := '1';
idata_oe := '1';
if idly_end = '1' then
idata_ceo := '0';
itxfifo_hold := '0';
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_wrpwh;
else
islwr := '1';
n.state := s_wrpwl;
end if;
when s_wrpwh => -- s_wrpwh: write, strobe high
idata_oe := '1';
if idly_end = '1' then
if iflag_wrok='1' and TXFIFO_VAL='1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_peprep => -- s_peprep: prepare pktend
if idly_end = '1' then
if iflag_wrok = '1' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_pepwl => -- s_pepwl: pktend, strobe low
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_pepwh;
else
ipktend := '1';
n.state := s_pepwl;
end if;
when s_pepwh => -- s_pepwh: pktend, strobe high
if idly_end = '1' then
n.pepend := '0';
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when others => null;
end case;
if idly_ld = '1' then
n.dlycnt := idly_val;
elsif idly_end = '0' then
n.dlycnt := slv(unsigned(r.dlycnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or
r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
else
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
end if;
imoni.fifo_ep4 := r.moni_ep4_sel;
imoni.fifo_ep6 := r.moni_ep6_sel;
imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef);
imoni.flag_ep4_almost := r.moni_ep4_pf;
imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff);
imoni.flag_ep6_almost := r.moni_ep6_pf;
imoni.slrd := islrd;
imoni.slwr := islwr;
imoni.pktend := ipktend;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
MONI <= imoni;
end process proc_next;
proc_almost: process (RXSIZE, TXSIZE)
begin
-- (rx|tx)size is the number of bytes in fifo
-- --> rxsize is number of bytes which can be read
-- --> 2**txfawidth-txsize is is number of bytes which can be written
if unsigned(RXSIZE) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
end syn;

13
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# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
../../vlib/memlib/memlib.vhd
fx2lib.vhd
# components
../../vlib/xlib/iob_reg_o.vbom
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
../../vlib/memlib/fifo_2c_dram.vbom
# design
fx2_2fifoctl_ic.vhd

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-- $Id: fx2_2fifoctl_ic.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101 173 64 159 s 8.3/7.4
-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows
-- 2012-01-09 451 1.0 Initial version
-- 2012-01-01 448 0.5 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_ic;
architecture syn of fx2_2fifoctl_ic is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe drain
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp -- s_txdisp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
rxpipe : slbit; -- read transaction in flight
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
'0','0', -- pepend,rxpipe
ccnt_init, -- ccnt
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS,
FX2_FLAG_N, TXFIFO_VAL, RXSIZE_FX2,
RXFIFO_BUSY, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable pipeok : slbit := '0';
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
imoni := fx2ctl_moni_init;
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and RXFIFO_BUSY='0' then
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
end if;
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
if r.rxpipe = '1' then -- read in flight ?
irxfifo_ena := '1'; -- capture rxdata
n.rxpipe := '0';
end if;
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
n.state := s_txprep0;
-- if more rx to do and possible
elsif slrxok='1' and RXFIFO_BUSY='0' then
cc_cnt := '1';
idata_cei := '1';
islrd := '1';
if false and pipeok='1' and unsigned(RXSIZE_FX2)>2 then
n.rxpipe := '1';
n.state := s_rxdisp;
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when s_rxpipe => -- s_rxpipe: read, pipe drain
isloe := '1';
irxfifo_ena := '1'; -- capture rxdata
if pipeok='1' and unsigned(RXSIZE_FX2)>1 then
n.state := s_rxdisp;
else
n.state := s_rxprep2;
end if;
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
end if;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
end process proc_next;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
R_MONI_S <= R_MONI_C;
end if;
end if;
end process proc_moni;
proc_almost: process (RXSIZE_USR, TXSIZE_USR)
begin
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
MONI <= R_MONI_S;
end syn;

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rtl/bplib/fx2lib/fx2_3fifoctl_ic.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
../../vlib/memlib/memlib.vhd
fx2lib.vhd
# components
../../vlib/xlib/iob_reg_o.vbom
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
../../vlib/memlib/fifo_2c_dram.vbom
# design
fx2_3fifoctl_ic.vhd

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rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd Normal file
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-- $Id: fx2_3fifoctl_ic.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_3fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 driver (3 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-15 453 13.3 O76x xc3s1200e-4 156 259 96 238 s 7.9/7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-09 453 1.0 Initial version (derived from 2fifo_ic)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_3fifoctl_ic;
architecture syn of fx2_3fifoctl_ic is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_tx2fifo: slv2 := c_fifo_ep8;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe drain
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp, -- s_txdisp: write, dispatch
s_tx2prep0, -- s_tx2prep0: switch to tx2-fifo
s_tx2prep1, -- s_tx2prep1: fifo addr setup
s_tx2prep2, -- s_tx2prep2: wait for flags
s_tx2disp -- s_tx2disp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend 1 time out counter
pe2tocnt : slv(PETOWIDTH-1 downto 0); -- pktend 2 time out counter
pepend : slbit; -- pktend 1 pending
pe2pend : slbit; -- pktend 2 pending
rxpipe : slbit; -- read transaction in flight
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep8_sel : slbit; -- ep8 (tx2) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
moni_ep8_pf : slbit; -- ep8 (tx2) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
petocnt_init, -- pe2tocnt
'0','0','0', -- pepend,pe2pend,rxpipe
ccnt_init, -- ccnt
'0','0','0', -- moni_ep(4|6|8)_sel
'0','0','0' -- moni_ep(4|6|8)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal FX2_DATA_DO : slv8 := (others=>'0');
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2FIFO_DO : slv8 := (others=>'0');
signal TX2FIFO_VAL : slbit := '0';
signal TX2FIFO_HOLD : slbit := '0';
signal TX2SIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2SIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
signal TX2BUSY_L : slbit := '0';
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1 and
TX2AFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL|TX2AFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => FX2_DATA_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
TX2FIFO : fifo_2c_dram -- output 2 fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TX2DATA,
ENA => TX2ENA,
BUSY => TX2BUSY_L,
DO => TX2FIFO_DO,
VAL => TX2FIFO_VAL,
HOLD => TX2FIFO_HOLD,
SIZEW => TX2SIZE_USR,
SIZER => TX2SIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS,
FX2_FLAG_N, TXFIFO_VAL, TX2FIFO_VAL,
TXFIFO_DO, TX2FIFO_DO,
RXSIZE_FX2, RXFIFO_BUSY, TXBUSY_L, TX2BUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable itx2fifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable idata_do : slv8 := (others=>'0');
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable sltx2ok : slbit := '0';
variable pipeok : slbit := '0';
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
itx2fifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
idata_do := TXFIFO_DO;
imoni := fx2ctl_moni_init;
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
sltx2ok := FX2_FLAG_N(c_flag_tx2_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and RXFIFO_BUSY='0' then
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
elsif sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')then
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
end if;
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
if r.rxpipe = '1' then -- read in flight ?
irxfifo_ena := '1'; -- capture rxdata
n.rxpipe := '0';
end if;
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
n.state := s_txprep0;
-- if chunk done and tx2 or pe2 pending and possible
elsif cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
n.state := s_tx2prep0;
-- if more rx to do and possible
elsif slrxok='1' and RXFIFO_BUSY='0' then
cc_cnt := '1';
idata_cei := '1';
islrd := '1';
if false and pipeok='1' and unsigned(RXSIZE_FX2)>2 then
n.rxpipe := '1';
n.state := s_rxdisp;
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when s_rxpipe => -- s_rxpipe: read, pipe drain
isloe := '1';
irxfifo_ena := '1'; -- capture rxdata
if pipeok='1' and unsigned(RXSIZE_FX2)>1 then
n.state := s_rxdisp;
else
n.state := s_rxprep2;
end if;
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and tx2 or pe2 pending and possible
if cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
n.state := s_tx2prep0;
-- if chunk done and rx pending and possible
elsif cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_do := TXFIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when s_tx2prep0 => -- s_tx2prep0: switch to tx2-fifo
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
when s_tx2prep1 => -- s_tx2prep1: fifo addr setup
cc_clr := '1';
n.state := s_tx2prep2;
when s_tx2prep2 => -- s_tx2prep2: wait for flags
n.state := s_tx2disp;
when s_tx2disp => -- s_tx2disp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if chunk done and tx or pe pending and possible
elsif cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')
then
n.state := s_txprep0;
-- if pktend 2 to do and possible
elsif sltx2ok = '1' and r.pe2pend = '1' then
ipktend := '1';
n.pe2pend := '0';
n.state := s_idle;
-- if more tx2 to do and possible
elsif sltx2ok = '1' and TX2FIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pe2pend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itx2fifo_hold := '0';
idata_do := TX2FIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_tx2disp; -- stream
else
n.state := s_tx2prep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
if TX2FIFO_VAL = '1' then
n.pe2tocnt := (others=>'1');
else
if unsigned(r.pe2tocnt) /= 0 then
n.pe2tocnt := slv(unsigned(r.pe2tocnt) - 1);
if unsigned(r.pe2tocnt) = 1 then
n.pe2pend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
n.moni_ep8_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_tx2disp then
n.moni_ep8_sel := '1';
n.moni_ep8_pf := not FX2_FLAG_N(c_flag_prog);
end if;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
FX2_DATA_DO <= idata_do;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
TX2FIFO_HOLD <= itx2fifo_hold;
end process proc_next;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.fifo_ep8 <= R_REGS.moni_ep8_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.flag_ep8_full <= not FX2_FLAG_N(c_flag_tx2_ff);
R_MONI_C.flag_ep8_almost <= R_REGS.moni_ep8_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
R_MONI_S <= R_MONI_C;
end if;
end if;
end process proc_moni;
proc_almost: process (RXSIZE_USR, TXSIZE_USR, TX2SIZE_USR)
begin
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
if unsigned(TX2SIZE_USR) <= TX2AFULL_THRES then
TX2AFULL <= '1';
else
TX2AFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
TX2BUSY <= TX2BUSY_L;
MONI <= R_MONI_S;
end syn;

172
rtl/bplib/fx2lib/fx2lib.vhd Normal file
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@@ -0,0 +1,172 @@
-- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: fx2lib
-- Description: Cypress ez-usb fx2 support
--
-- Dependencies: -
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as
-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type
-- 2011-07-07 389 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package fx2lib is
constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2
constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4
constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6
constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8
type fx2ctl_moni_type is record -- fx2ctl monitor port
fifo_ep4 : slbit; -- fifo 1 (ep4) active;
fifo_ep6 : slbit; -- fifo 2 (ep6) active;
fifo_ep8 : slbit; -- fifo 3 (ep8) active;
flag_ep4_empty : slbit; -- ep4 empty flag (latched);
flag_ep4_almost : slbit; -- ep4 almost empty flag (latched);
flag_ep6_full : slbit; -- ep6 full flag (latched);
flag_ep6_almost : slbit; -- ep6 almost full flag (latched);
flag_ep8_full : slbit; -- ep8 full flag (latched);
flag_ep8_almost : slbit; -- ep8 almost full flag (latched);
slrd : slbit; -- read strobe
slwr : slbit; -- write strobe
pktend : slbit; -- pktend strobe
end record fx2ctl_moni_type;
constant fx2ctl_moni_init : fx2ctl_moni_type := (
'0','0','0', -- fifo_ep[468]
'0','0', -- flag_ep4_(empty|almost)
'0','0', -- flag_ep6_(full|almost)
'0','0', -- flag_ep8_(full|almost)
'0','0','0' -- slrd, slwr, pktend
);
-- -------------------------------------
component fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package fx2lib;

7
rtl/bplib/nexys2/nexys2_pins.ucf
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@@ -1,4 +1,4 @@
## $Id: nexys2_pins.ucf 432 2011-11-25 20:16:28Z mueller $
## $Id: nexys2_pins.ucf 444 2011-12-25 10:04:58Z mueller $
##
## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
## - internal RS232
@@ -7,6 +7,7 @@
##
## Revision History:
## Date Rev Version Comment
## 2011-11-23 444 1.1 remove clksys output hack
## 2010-11-13 338 1.0.3 add O_CLKSYS (for DCM derived system clock)
## 2010-11-06 336 1.0.2 Rename CLK -> I_CLK50
## 2010-05-23 294 1.0.1 use ADV_N rather ADV
@@ -17,10 +18,6 @@
## clocks --------------------------------------------------------------------
NET "I_CLK50" LOC = "b8" | IOSTANDARD=LVCMOS33;
##
## system clock on FX2 connector ---------------------------------------------
## (use FX2_CLKIO pin; currently only used to make test benches happy !!)
NET "O_CLKSYS" LOC = "m9" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
##
## RS232 interface -----------------------------------------------------------
NET "I_RXD" LOC = "u6" | IOSTANDARD=LVCMOS33;
NET "O_TXD" LOC = "p9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;

36
rtl/bplib/nexys2/nexys2_pins_fx2.ucf Normal file
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@@ -0,0 +1,36 @@
## $Id: nexys2_pins_fx2.ucf 397 2011-07-24 09:43:07Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-07-05 389 1.0 Initial version
##
## Cypress EZ-USB FX2 Interface ----------------------------------------------
##
##
NET "I_FX2_IFCLK" LOC = "t15" | IOSTANDARD=LVCMOS33;
##
NET "IO_FX2_DATA<0>" LOC = "r14" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<1>" LOC = "r13" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<2>" LOC = "p13" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<3>" LOC = "t12" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<4>" LOC = "n11" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<5>" LOC = "r11" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<6>" LOC = "p10" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<7>" LOC = "r10" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
NET "O_FX2_SLWR_N" LOC = "v9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLRD_N" LOC = "n9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLOE_N" LOC = "v15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_PKTEND_N" LOC = "v12" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_FIFO<0>" LOC = "t14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_FIFO<1>" LOC = "v13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
## assume that PA.7 is used a FLAGD (and not as SLCS#)
NET "I_FX2_FLAG<0>" LOC = "v14" | IOSTANDARD=LVCMOS33; ## flag a (program)
NET "I_FX2_FLAG<1>" LOC = "u14" | IOSTANDARD=LVCMOS33; ## flag b (full)
NET "I_FX2_FLAG<2>" LOC = "v16" | IOSTANDARD=LVCMOS33; ## flag c (empty)
NET "I_FX2_FLAG<3>" LOC = "t16" | IOSTANDARD=LVCMOS33; ## flag d (slcs)
##

26
rtl/bplib/nexys2/nexys2_time_fx2_ic.ucf Normal file
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@@ -0,0 +1,26 @@
## $Id: nexys2_time_fx2_ic.ucf 448 2012-01-02 21:55:11Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2012-01-01 448 1.0 Initial version
##
## timing rules for a 30 MHz internal clock design:
## Period: 30 MHz
## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
## clk->out < 33.3-18.7 = 14.6 ns
## --> use 10 ns
##
## The nexys2 board has unfortunately the FX2 IFCLK *not* connected to a
## clock capable pin -> not ok when FX2 uses internal clock. So allow par
## to route from a 'normal' pin to a clock net. Not nice, compromizes the
## timing, but unavoidable on nexys2 (Note: nexys3 and atlys are ok).
## In practice IFCLK to pad times are quite similar on nexys2 and nexys3...
NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
##
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2.5 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns AFTER "I_FX2_IFCLK";

74
rtl/bplib/nexys2/nexys2lib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: nexys2lib.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: nexys2lib.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,6 +20,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.4 add nexys2_cuff_aif, nexys2_fusp_cuff_aif
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram driver/dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
@@ -40,7 +42,6 @@ package nexys2lib is
component nexys2_aif is -- NEXYS 2, abstract iface, base
port (
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
@@ -65,7 +66,6 @@ end component;
component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
port (
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
@@ -91,4 +91,72 @@ component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
);
end component;
component nexys2_cuff_aif is -- NEXYS 2, abstract iface, base+cuff
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component nexys2_fusp_cuff_aif is -- NEXYS 2, abstract iface, +fusp+cuff
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package nexys2lib;

7
rtl/bplib/nexys2/tb/Makefile
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@@ -1,14 +1,17 @@
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
# $Id: Makefile 467 2013-01-02 19:49:05Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-01-01 467 1.2.1 add tb_nexys2_fusp_cuff_dummy
# 2011-11-26 433 1.2 remove tb_n2_cram_memctl_as (moved to nxcramlib)
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now
# 2010-05-28 295 1.0.1 add tb_.._dummy's
# 2007-09-23 84 1.0 Initial version
#
EXE_all = tb_nexys2_dummy tb_nexys2_fusp_dummy
EXE_all = tb_nexys2_dummy
EXE_all += tb_nexys2_fusp_dummy
EXE_all += tb_nexys2_fusp_cuff_dummy
#
ISE_PATH = xc3s1200e-fg320-4
#

7
rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd
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@@ -1,4 +1,4 @@
-- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: nexys2_fusp_dummy.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -12,7 +12,7 @@
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Module Name: nexys2_fusp_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
@@ -22,6 +22,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
@@ -39,7 +40,6 @@ entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
@@ -69,7 +69,6 @@ architecture syn of nexys2_fusp_dummy is
begin
O_CLKSYS <= I_CLK50; -- use 50 MHz clock
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;

9
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
View File

@@ -7,14 +7,19 @@
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/xlib/xlib.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
nexys2_fusp_aif : nexys2_fusp_dummy.vbom
${nexys2_fusp_aif := nexys2_fusp_dummy.vbom}
# design
tb_nexys2_fusp.vhd
@top:tb_nexys2_fusp

72
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
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@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tb_nexys2_fusp.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,9 +15,12 @@
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys2_core
-- vlib/serport/serport_uart_rxtx
-- serport/serport_uart_rxtx
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
@@ -27,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
@@ -46,9 +50,11 @@ use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
@@ -56,7 +62,10 @@ end tb_nexys2_fusp;
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
@@ -105,27 +114,42 @@ architecture sim of tb_nexys2_fusp is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 20 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
begin
TBCORE : tbcore_rlink_dcm
CLKGEN : simclk
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
@@ -149,7 +173,6 @@ begin
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
O_CLKSYS => CLKSYS,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
@@ -178,7 +201,7 @@ begin
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
@@ -217,11 +240,10 @@ begin
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;

7
rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom
View File

@@ -1,7 +0,0 @@
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys3_fusp_dummy.vhd

90
rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd
View File

@@ -1,90 +0,0 @@
-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 use nxcramlib
-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys3_fusp_dummy;
architecture syn of nexys3_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;

8
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
View File

@@ -11,13 +11,15 @@
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
sys_conf : sys_conf_sim.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
nexys3_fusp_aif : nexys3_fusp_dummy.vbom
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}
# design
tb_nexys3_fusp.vhd
@top:tb_nexys3_fusp

67
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tb_nexys3_fusp.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,10 +15,12 @@
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- vlib/xlib/dcm_sfs
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- vlib/serport/serport_uart_rxtx
-- serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
@@ -28,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
@@ -52,8 +55,11 @@ end tb_nexys3_fusp;
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
@@ -103,40 +109,44 @@ architecture sim of tb_nexys3_fusp is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 10 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
TBCORE : tbcore_rlink_dcm
CLKGEN : simclk
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
DCM_SYS : dcm_sfs
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKSYS,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N3CORE : entity work.tb_nexys3_core
@@ -187,7 +197,7 @@ begin
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
@@ -226,11 +236,10 @@ begin
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;

3
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom
View File

@@ -7,8 +7,9 @@
../../../vlib/simlib/simlib.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../micron/mt45w8mw16b.vbom
uut : tbd_nx_cram_memctl_as.vbom
${uut := tbd_nx_cram_memctl_as.vbom}
# design
tb_nx_cram_memctl.vhd
@top:tb_nx_cram_memctl

11
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nx_cram_memctl.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,6 +16,7 @@
-- Description: Test bench for nx_cram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/micron/mt45w8mw16b
-- tbd_nx_cram_memctl [UUT, abstact]
--
@@ -25,6 +26,7 @@
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl
-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl
@@ -109,7 +111,7 @@ end component;
signal R_REF_ADDR_DL : slv22 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
@@ -118,16 +120,17 @@ end component;
begin
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,

6
rtl/bplib/s3board/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
# $Id: Makefile 444 2011-12-25 10:04:58Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -9,7 +9,9 @@
# 2007-11-26 98 1.1 use make includes
# 2007-09-23 84 1.0 Initial version
#
EXE_all = tb_s3board_dummy tb_s3board_fusp_dummy tb_s3_sram_memctl
EXE_all = tb_s3board_dummy
EXE_all += tb_s3board_fusp_dummy
EXE_all += tb_s3_sram_memctl
#
ISE_PATH = xc3s1000-ft256-4
#

3
rtl/bplib/s3board/tb/tb_s3_sram_memctl.vbom
View File

@@ -4,7 +4,8 @@
../../../vlib/simlib/simlib.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../issi/is61lv25616al.vbom
uut : ../s3_sram_memctl.vbom
${uut := ../s3_sram_memctl.vbom}
# design
tb_s3_sram_memctl.vhd

11
rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3_sram_memctl.vhd 432 2011-11-25 20:16:28Z mueller $
-- $Id: tb_s3_sram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,6 +16,7 @@
-- Description: Test bench for s3_sram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/issi/is61lv25616al
-- s3_sram_memctl [UUT]
--
@@ -30,6 +31,7 @@
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-11-21 432 1.0.6 now numeric_std clean
-- 2010-05-23 293 1.0.5 output # busy cycles; change CHK pipeline logic
-- 2010-05-16 291 1.0.4 rename tb_memctl_s3sram->tb_s3_sram_memctl
@@ -86,7 +88,7 @@ architecture sim of tb_s3_sram_memctl is
signal R_REF_ADDR_DL : slv18 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
@@ -95,16 +97,17 @@ architecture sim of tb_s3_sram_memctl is
begin
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),

4
rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
View File

@@ -11,10 +11,12 @@
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
tb_s3board_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
s3board_fusp_aif : s3board_fusp_dummy.vbom
${s3board_fusp_aif := s3board_fusp_dummy.vbom}
# design
tb_s3board_fusp.vhd
@top:tb_s3board_fusp

48
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3board_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: tb_s3board_fusp.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,10 +15,12 @@
-- Module Name: tb_s3board_fusp - sim
-- Description: Test bench for s3board (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- tb_s3board_core
-- vlib/serport/serport_uart_rxtx
-- s3board_fusp_aif [UUT]
-- serport/serport_uart_rxtx
--
-- To test: generic, any s3board_fusp_aif target
--
@@ -26,6 +28,7 @@
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
@@ -55,6 +58,9 @@ end tb_s3board_fusp;
architecture sim of tb_s3board_fusp is
signal CLK : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
@@ -100,24 +106,29 @@ architecture sim of tb_s3board_fusp is
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
TBCORE : tbcore_rlink
CLKGEN : simclk
generic map (
CLK_PERIOD => clock_period,
CLK_OFFSET => clock_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLK,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
@@ -200,10 +211,9 @@ begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;

48
rtl/make/generic_xflow.mk
View File

@@ -1,7 +1,11 @@
# $Id: generic_xflow.mk 406 2011-08-14 21:06:44Z mueller $
# $Id: generic_xflow.mk 456 2012-02-05 22:19:44Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-02-05 456 1.7.5 use vbomvonv --get_top for xflow calls
# 2012-01-08 451 1.7.4 use xilinx_ghdl_sdf_filter
# 2012-01-04 450 1.7.3 display isemsg_filter for ncd and bit targets too
# 2011-12-29 446 1.7.2 add fx2load_wrapper in jconfig target
# 2011-08-14 406 1.7.1 use isemsg_filter; new %.mfsum target
# 2011-08-13 405 1.7 renamed, moved to rtl/make;
# 2011-07-17 394 1.6.2 add rm *.svf to ise_clean rule
@@ -78,7 +82,8 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
-g top_entity:`vbomconv --get_top $<` $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@@ -99,7 +104,8 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
-g top_entity:`vbomconv --get_top $<` $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@@ -137,6 +143,21 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ./ise/$*.par ]; then cp -p ./ise/$*.par ./$*_par.log; fi
if [ -r ./ise/$*_pad.txt ]; then cp -p ./ise/$*_pad.txt ./$*_pad.log; fi
if [ -r ./ise/$*.twr ]; then cp -p ./ise/$*.twr ./$*_twr.log; fi
@ if [ -r $*.mfset ]; then \
echo "=============================================================";\
echo "* Translate Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter tra $*.mfset $*_tra.log;\
echo "=============================================================";\
echo "* MAP Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter map $*.mfset $*_map.log;\
echo "=============================================================";\
echo "* PAR Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter par $*.mfset $*_par.log;\
echo "=============================================================";\
fi
#
# Implement 2 (bitgen)
# input: %.ncd
@@ -152,6 +173,13 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ./ise/$*.bit ]; then cp -p ./ise/$*.bit .; fi
if [ -r ./ise/$*.msk ]; then cp -p ./ise/$*.msk .; fi
if [ -r ./ise/$*.bgn ]; then cp -p ./ise/$*.bgn ./$*_bgn.log; fi
@ if [ -r $*.mfset ]; then \
echo "=============================================================";\
echo "* Bitgen Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter bgn $*.mfset $*_bgn.log;\
echo "=============================================================";\
fi
#
# Create svf from bitstream
# input: %.bit
@@ -173,7 +201,12 @@ XFLOW = xflow -p ${ISE_PATH}
# input: %.svf
# output: .PHONY
#
ifneq "$(origin FX2_FILE)" "undefined"
FX2LOAD_OPT = --file=${FX2_FILE}
endif
#
%.jconfig: %.svf
fx2load_wrapper --board=${ISE_BOARD} ${FX2LOAD_OPT}
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} jconfig $*.svf
#
@@ -225,9 +258,12 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ./ise/$*.nlf ]; then cp -p ./ise/$*.nlf ./$*_ngn_fsim.log; fi
#
# Post-par timing simulation model (netgen -sim)
# input: %.ncd
# input: %.ncd
# %.tsim_xon_dat xon disable descriptor file (optional)
# output: %_tsim.vhd
# %_ngn_tsim.log netgen log file (renamed time_sim.nlf)
# %_ngn_tsim.log netgen log file (renamed time_sim.nlf)
# %_tsim.sdf delay annotation
# %_tsim.sdf_ghdl delay annotation with ghdl patches
#
#!! use netgen directly because xflow 8.1 goes mad when -tsim used a 2nd time
#!! see blog_xilinx_webpack.txt 2007-06-10
@@ -243,6 +279,7 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ./ise/$*_tsim.sdf ]; then cp -p ./ise/$*_tsim.sdf .; fi
if [ -r ./ise/$*_tsim.nlf ]; then cp -p ./ise/$*_tsim.nlf ./$*_ngn_tsim.log; fi
if [ -r $*_tsim.vhd -a -r $*.tsim_xon_dat ]; then xilinx_tsim_xon $*; fi
if [ -r $*_tsim.sdf ]; then xilinx_ghdl_sdf_filter $*_tsim.sdf > $*_tsim.sdf_ghdl ; fi
#
# generate dep_xst files from vbom
#
@@ -271,6 +308,7 @@ ise_clean: ise_tmp_clean
rm -rf *.svf
rm -rf *_[sft]sim.vhd
rm -rf *_tsim.sdf
rm -rf *_tsim.sdf_ghdl
rm -rf *_xst.log
rm -rf *_tra.log
rm -rf *_map.log

7
rtl/make/imp_s6_speed.opt
View File

@@ -1,10 +1,11 @@
FLOWTYPE = FPGA;
#
# $Id: imp_s6_speed.opt 405 2011-08-14 08:16:28Z mueller $
# $Id: imp_s6_speed.opt 449 2012-01-04 08:14:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.0 Initial version
# 2012-01-03 449 1.1 use '-mt 2' in map and par
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE balanced.opt
# Uses uses settings like 'mapgloboptlogoptregdup' SmartExplorer strategy
@@ -39,6 +40,7 @@ Program map
-logic_opt on; # Perform physical synthesis combinatorial logic opt.
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-w; # Always overwrite any existing output files
-mt 2; # Multi-threading
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
@@ -69,6 +71,7 @@ Program par
-ol high; # Overall effort level
-xe n; # extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-mt 2; # Multi-threading
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file

7
rtl/make/syn_s6_speed.opt
View File

@@ -1,9 +1,10 @@
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s6_speed.opt 405 2011-08-14 08:16:28Z mueller $
# $Id: syn_s6_speed.opt 456 2012-02-05 22:19:44Z mueller $
#
# Revision History:
# Date Rev Version Comment
# Date Rev Version Comment
# 2012-02-05 456 1.1 use $top_entity variable for -top attribute
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE xst_mixed.opt
@@ -27,7 +28,7 @@ ParamFile: <design>_xst.scr
"-ifmt mixed"; # Input Format (Verilog and VHDL)
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-top <design>"; # Top Design Name
"-top $top_entity"; # Top Design Name
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High

2
rtl/sys_gen/tst_fx2loop/.cvsignore Normal file
View File

@@ -0,0 +1,2 @@
tst_fx2loop
tst_fx2loop_si

34
rtl/sys_gen/tst_fx2loop/Makefile Normal file
View File

@@ -0,0 +1,34 @@
# $Id: Makefile 461 2012-04-09 21:17:54Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-02-26 458 1.1 add tst_fx2loop_si
# 2011-12-26 445 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all clean realclean
#
all : tst_fx2loop tst_fx2loop_si
#
clean : ise_clean
#
realclean :
rm -f tst_fx2loop tst_fx2loop_si
#
CFLAGS = -Wall -O2 -g -lusb-1.0
#
tst_fx2loop : tst_fx2loop.c
${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c
tst_fx2loop_si : tst_fx2loop_si.c
${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#

4
rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore Normal file
View File

@@ -0,0 +1,4 @@
_impactbatch.log
sys_tst_fx2loop_ic_n2.ucf
*.dep_ucf_cpp
*.svf

29
rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile Normal file
View File

@@ -0,0 +1,29 @@
# $Id: Makefile 453 2012-01-15 17:51:18Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-01-15 453 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
FX2_FILE = nexys2_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

58
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd Normal file
View File

@@ -0,0 +1,58 @@
-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

63
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset Normal file
View File

@@ -0,0 +1,63 @@
# $Id: sys_tst_fx2loop_ic_n2.mfset 453 2012-01-15 17:51:18Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Node <TST/R_REGS.tx2data_\d*> of sequential type is unconnected
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS\..*_\d> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.datl_\d*> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.dath_\d*> of sequential type is unconnected
Signal <FX2_TX2DATA> is assigned but never used
Input <BTN> is never used
Input <SWI<4>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <I_MEM_WAIT> is never used
Signal <TXODD> is assigned but never used
Signal <TX2ODD> is assigned but never used
Signal <RXODD> is assigned but never used
#
# ----------------------------------------------------------------------------
[tra]
INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
The Offset constraint .*, is specified without a duration
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
A clock IOB / clock component pair have been found that are not placed at
The Offset constraint .*, is specified without a duration
The signal I_MEM_WAIT_IBUF has no load
The signal I_BTN<1>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are 4 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
To achieve optimal frequency synthesis performance .* consult
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete

15
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp Normal file
View File

@@ -0,0 +1,15 @@
## $Id: sys_tst_fx2loop_ic_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-12-26 445 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
#include "bplib/nexys2/nexys2_pins.ucf"
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom Normal file
View File

@@ -0,0 +1,8 @@
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n2.vbom
@ucf_cpp: sys_tst_fx2loop_ic_n2.ucf
@top: sys_tst_fx2loop_n2

4
rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore Normal file
View File

@@ -0,0 +1,4 @@
_impactbatch.log
sys_tst_fx2loop_ic3_n2.ucf
*.dep_ucf_cpp
*.svf

29
rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile Normal file
View File

@@ -0,0 +1,29 @@
# $Id: Makefile 453 2012-01-15 17:51:18Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-01-15 453 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
FX2_FILE = nexys2_jtag_3fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

58
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd Normal file
View File

@@ -0,0 +1,58 @@
-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
constant sys_conf_fx2_type : string := "ic3";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

58
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset Normal file
View File

@@ -0,0 +1,58 @@
# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS\..*_\d> of sequential type is unconnected
Input <BTN> is never used
Input <SWI<4>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <I_MEM_WAIT> is never used
Signal <TXODD> is assigned but never used
Signal <TX2ODD> is assigned but never used
Signal <RXODD> is assigned but never used
#
# ----------------------------------------------------------------------------
[tra]
INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
The Offset constraint .*, is specified without a duration
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
A clock IOB / clock component pair have been found that are not placed at
The Offset constraint .*, is specified without a duration
The signal I_MEM_WAIT_IBUF has no load
The signal I_BTN<1>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are 4 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
To achieve optimal frequency synthesis performance .* consult
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete

15
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp Normal file
View File

@@ -0,0 +1,15 @@
## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-12-26 445 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
#include "bplib/nexys2/nexys2_pins.ucf"
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom Normal file
View File

@@ -0,0 +1,8 @@
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n2.vbom
@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf
@top: sys_tst_fx2loop_n2

30
rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom Normal file
View File

@@ -0,0 +1,30 @@
# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./as/sys_tst_fx2loop_as_n2
# ./ic/sys_tst_fx2loop_ic_n2
# ./ic3/sys_tst_fx2loop_ic3_n2
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../tst_fx2looplib.vbom
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_fx2loop_hiomap.vbom
../tst_fx2loop.vbom
../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_fx2loop_n2.vhd
## no @ucf_cpp

354
rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd Normal file
View File

@@ -0,0 +1,354 @@
-- $Id: sys_tst_fx2loop_n2.vhd 461 2012-04-09 21:17:54Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n2 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100
-- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_fx2loop_n2 is -- top level
-- implements nexys2_aif + fx2 pins
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n2;
architecture syn of sys_tst_fx2loop_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN,
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;

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# libs
../../vlib/slvtypes.vhd
../../vlib/comlib/comlib.vhd
../../bplib/fx2lib/fx2lib.vhd
tst_fx2looplib.vhd
# components
../../vlib/comlib/byte2word.vbom
../../vlib/comlib/word2byte.vbom
# design
tst_fx2loop.vhd

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-- $Id: tst_fx2loop.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop - syn
-- Description: simple stand-alone tester for fx2lib components
--
-- Dependencies: comlib/byte2word
-- comlib/word2byte
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
-- 2011-12-26 445 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
-- ----------------------------------------------------------------------------
entity tst_fx2loop is -- tester for fx2lib components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit; -- transmit busy
TX2DATA : out slv8; -- transmit 2 data in
TX2ENA : out slbit; -- transmit 2 data enable
TX2BUSY : in slbit -- transmit 2 busy
);
end tst_fx2loop;
architecture syn of tst_fx2loop is
type regs_type is record
rxdata : slv16; -- next rx word
txdata : slv16; -- next tx word
tx2data : slv16; -- next tx2 word
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx word counter
txcnt : slv32; -- tx word counter
tx2cnt : slv32; -- tx2 word counter
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- tx2data
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- tx2cnt
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RXWDATA : slv16 := (others=>'0');
signal RXWVAL : slbit := '0';
signal RXWHOLD : slbit := '0';
signal RXODD : slbit := '0';
signal TXWDATA : slv16 := (others=>'0');
signal TXWENA : slbit := '0';
signal TXWBUSY : slbit := '0';
signal TXODD : slbit := '0';
signal TX2WDATA : slv16 := (others=>'0');
signal TX2WENA : slbit := '0';
signal TX2WBUSY : slbit := '0';
signal TX2ODD : slbit := '0';
signal RXHOLD_L : slbit := '0'; -- local copy of out port signal
signal TXENA_L : slbit := '0'; -- local copy of out port signal
signal TX2ENA_L : slbit := '0'; -- local copy of out port signal
signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal
begin
CNTL_RESET_L <= '0'; -- so far unused
RXB2W : byte2word
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => RXDATA,
ENA => RXVAL,
BUSY => RXHOLD_L,
DO => RXWDATA,
VAL => RXWVAL,
HOLD => RXWHOLD,
ODD => RXODD
);
TX1W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TXWDATA,
ENA => TXWENA,
BUSY => TXWBUSY,
DO => TXDATA,
VAL => TXENA_L,
HOLD => TXBUSY,
ODD => TXODD
);
TX2W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TX2WDATA,
ENA => TX2WENA,
BUSY => TX2WBUSY,
DO => TX2DATA,
VAL => TX2ENA_L,
HOLD => TX2BUSY,
ODD => TX2ODD
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI,
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxwhold : slbit := '1';
variable itxwena : slbit := '0';
variable itxwdata : slv16 := (others=>'0');
variable itx2wena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irxwhold := '1';
itxwena := '0';
itxwdata := RXWDATA;
itx2wena := '0';
if HIO_CNTL.throttle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXWVAL='1' and r.rxthrottle='0' then
irxwhold := '0';
if RXWDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := slv(unsigned(RXWDATA) + 1);
end if;
when c_mode_txblast =>
itxwdata := r.txdata;
if TXWBUSY = '0' then
itxwena := '1';
n.txdata := slv(unsigned(r.txdata) + 1);
end if;
irxwhold := '0';
when c_mode_loop =>
itxwdata := RXWDATA;
if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then
irxwhold := '0';
itxwena := '1';
end if;
when others => null;
end case;
if HIO_CNTL.tx2blast = '1' then
if TX2WBUSY = '0' then
itx2wena := '1';
n.tx2data := slv(unsigned(r.tx2data) + 1);
end if;
end if;
if RXWVAL='1' and irxwhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxwena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
if itx2wena = '1' then
n.tx2cnt := slv(unsigned(r.tx2cnt) + 1);
end if;
N_REGS <= n;
RXWHOLD <= irxwhold;
TXWENA <= itxwena;
TXWDATA <= itxwdata;
TX2WENA <= itx2wena;
TX2WDATA <= r.tx2data;
HIO_STAT.rxhold <= RXHOLD_L;
HIO_STAT.txbusy <= TXBUSY;
HIO_STAT.tx2busy <= TX2BUSY;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.tx2cnt <= r.tx2cnt;
end process proc_next;
RXHOLD <= RXHOLD_L;
TXENA <= TXENA_L;
TX2ENA <= TX2ENA_L;
end syn;

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# libs
../../vlib/slvtypes.vhd
../../bplib/fx2lib/fx2lib.vhd
tst_fx2looplib.vbom
# components
# design
tst_fx2loop_hiomap.vhd

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-- $Id: tst_fx2loop_hiomap.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage
-- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3) -- unused --
-- (2) -- unused --
-- (1) -- unused --
-- (0) reset state [!! decoded by top level design !!]
--
-- SWI(7:5) select display
-- (4) -- unused --
-- (3) throttle
-- (2) tx2blast
-- (1:0) mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
--
-- LED(7) MONI.fifo_ep4
-- (6) MONI.fifo_ep6
-- (5) MONI.fifo_ep8
-- (4) MONI.flag_ep4_empty
-- (3) MONI.flag_ep4_almost
-- (2) MONI.flag_ep6_full
-- (1) MONI.flag_ep6_almost
-- (0) rxsecnt > 0 (sequence error)
--
-- DSP data as selected by SWI(7:5)
-- 000 -> rxsecnt
-- 001 -> -- unused -- (display ffff)
-- 010 -> rxcnt.l
-- 011 -> rxcnt.h
-- 100 -> txcnt.l
-- 101 -> txcnt.h
-- 110 -> tx2cnt.l
-- 111 -> tx2cnt.h
--
-- DP(3) FX2_TXBUSY (shows tx back preasure)
-- (2) FX2_MONI.slwr (shows tx activity)
-- (1) FX2_RXHOLD (shows rx back preasure)
-- (0) FX2_MONI.slrd (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
-- ----------------------------------------------------------------------------
entity tst_fx2loop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_fx2loop_hiomap;
architecture syn of tst_fx2loop_hiomap is
type regs_type is record
dspdat : slv16; -- display data
dummy : slbit; -- <remove when 2nd signal added...>
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- dspdat
'0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- setup tester controls
icntl.mode := SWI(1 downto 0);
icntl.tx2blast := SWI(2);
icntl.throttle := SWI(3);
-- setup leds
iled(7) := FX2_MONI.fifo_ep4;
iled(6) := FX2_MONI.fifo_ep6;
iled(5) := FX2_MONI.fifo_ep8;
iled(4) := FX2_MONI.flag_ep4_empty;
iled(3) := FX2_MONI.flag_ep4_almost;
iled(2) := FX2_MONI.flag_ep6_full;
iled(1) := FX2_MONI.flag_ep6_almost;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if;
-- setup display data
case SWI(7 downto 5) is
when "000" => idat := HIO_STAT.rxsecnt;
when "001" => idat := (others=>'1');
when "010" => idat := HIO_STAT.rxcnt(15 downto 0);
when "011" => idat := HIO_STAT.rxcnt(31 downto 16);
when "100" => idat := HIO_STAT.txcnt(15 downto 0);
when "101" => idat := HIO_STAT.txcnt(31 downto 16);
when "110" => idat := HIO_STAT.tx2cnt(15 downto 0);
when "111" => idat := HIO_STAT.tx2cnt(31 downto 16);
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := HIO_STAT.txbusy; -- tx back preasure
idp(2) := FX2_MONI.slwr; -- tx activity
idp(1) := HIO_STAT.rxhold; -- rx back preasure
idp(0) := FX2_MONI.slrd; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;

4
rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom Normal file
View File

@@ -0,0 +1,4 @@
# libs
../../vlib/slvtypes.vhd
../../bplib/fx2lib/fx2lib.vhd
tst_fx2looplib.vhd

109
rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd Normal file
View File

@@ -0,0 +1,109 @@
-- $Id: tst_fx2looplib.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: tst_fx2looplib
-- Description: Definitions for tst_fx2loop records and helpers
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.fx2lib.all;
package tst_fx2looplib is
constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as
constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic
constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
tx2blast : slbit; -- enable tx2 blast
throttle : slbit; -- enable 1 msec tx throttling
end record hio_cntl_type;
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0' -- tx2blast,throttle
);
type hio_stat_type is record -- humanio status
rxhold : slbit; -- rx hold
txbusy : slbit; -- tx busy
tx2busy : slbit; -- tx2 busy
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx word counter
txcnt : slv32; -- tx word counter
tx2cnt : slv32; -- tx2 word counter
end record hio_stat_type;
constant hio_stat_init : hio_stat_type := (
'0','0','0', -- rxhold,txbusy,tx2busy
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0') -- tx2cnt
);
-- -------------------------------------
component tst_fx2loop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit; -- transmit busy
TX2DATA : out slv8; -- transmit 2 data in
TX2ENA : out slbit; -- transmit 2 data enable
TX2BUSY : in slbit -- transmit 2 busy
);
end component;
component tst_fx2loop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
end package tst_fx2looplib;

4
rtl/sys_gen/tst_rlink/nexys2/Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -16,7 +16,7 @@ ISE_PATH = xc3s1200e-fg320-4
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_rlink_n2.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#

2
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom
View File

@@ -7,7 +7,7 @@
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom

29
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_rlink_n2.vhd 442 2011-12-23 10:03:28Z mueller $
-- $Id: sys_tst_rlink_n2.vhd 465 2012-12-27 21:29:38Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -31,6 +31,7 @@
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-12-27 453 13.3 O76d xc3s1200e-4 754 1605 96 1057 t 14.5
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8
-- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2
-- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8
@@ -38,6 +39,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 remove clksys output hack
-- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.1.5 use nx_cram_dummy now
-- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage
@@ -49,21 +51,21 @@
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- SWI(7:2) no function (only connected to sn_humanio_rbus)
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
@@ -85,7 +87,6 @@ entity sys_tst_rlink_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
@@ -162,8 +163,6 @@ begin
LOCKED => open
);
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,

2
rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom
View File

@@ -1,7 +1,7 @@
# configure tb_nexsy2_fusp with sys_tst_rlink_n2 target;
# use vhdl configure file (tb_tst_rlink_n2.vhd) to allow
# that all configurations will co-exist in work library
nexys2_aif : ../sys_tst_rlink_n2.vbom
${nexys2_aif := ../sys_tst_rlink_n2.vbom}
sys_conf = sys_conf_sim.vhd
../../../../bplib/nexys2/tb/tb_nexys2_fusp.vbom
tb_tst_rlink_n2.vhd

4
rtl/sys_gen/tst_rlink/nexys3/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -18,7 +18,7 @@ XFLOWOPT_IMP = imp_s6_speed.opt
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_rlink_n3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#

2
rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom
View File

@@ -7,7 +7,7 @@
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom

2
rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vbom
View File

@@ -1,7 +1,7 @@
# configure tb_nexsy3_fusp with sys_tst_rlink_n3 target;
# use vhdl configure file (tb_tst_rlink_n3.vhd) to allow
# that all configurations will co-exist in work library
nexys3_fusp_aif : ../sys_tst_rlink_n3.vbom
${nexys3_fusp_aif := ../sys_tst_rlink_n3.vbom}
sys_conf = sys_conf_sim.vhd
../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom
tb_tst_rlink_n3.vhd

4
rtl/sys_gen/tst_rlink/s3board/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -15,7 +15,7 @@ ISE_PATH = xc3s1000-ft256-4
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_rlink_s3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#

2
rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vbom
View File

@@ -6,7 +6,7 @@
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/s3board/s3boardlib.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom

2
rtl/sys_gen/tst_rlink/s3board/tb/tb_tst_rlink_s3.vbom
View File

@@ -1,7 +1,7 @@
# configure tb_s3board_fusp with sys_tst_rlink_s3 target;
# use vhdl configure file (tb_tst_rlink_s3.vhd) to allow
# that all configurations will co-exist in work library
s3board_aif : ../sys_tst_rlink_s3.vbom
${s3board_aif := ../sys_tst_rlink_s3.vbom}
sys_conf = sys_conf_sim.vhd
../../../../bplib/s3board/tb/tb_s3board_fusp.vbom
tb_tst_rlink_s3.vhd

24
rtl/sys_gen/tst_rlink_cuff/Makefile Normal file
View File

@@ -0,0 +1,24 @@
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-12-29 466 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all clean realclean
#
all : $(NGC_all)
#
clean : ise_clean
#
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#

4
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/.cvsignore Normal file
View File

@@ -0,0 +1,4 @@
_impactbatch.log
sys_tst_rlink_cuff_ic_n2.ucf
*.dep_ucf_cpp
*.svf

29
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile Normal file
View File

@@ -0,0 +1,29 @@
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-12-29 466 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
FX2_FILE = nexys2_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

62
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_conf.vhd Normal file
View File

@@ -0,0 +1,62 @@
-- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

104
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset Normal file
View File

@@ -0,0 +1,104 @@
# $Id: sys_tst_rlink_cuff_ic_n2.mfset 466 2012-12-30 13:26:55Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Register <R_MONI_C.fifo_ep8> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.flag_ep8_full> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.flag_ep8_almost> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.flag_ep8_almost> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.flag_ep8_full> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.fifo_ep8> in unit <fx2_2fifoctl_ic> has a constant value
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
Unconnected output port 'RL_MONI' of component 'rlink_core8'
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
Input <RB_MREQ.init> is never used
Input <BTN> is never used
Input <SWI<7:3>> is never used
Input <SWI<0>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <FX2_MONI.flag_ep4_empty> is never used
Input <FX2_MONI.flag_ep4_almost> is never used
Input <FX2_MONI.flag_ep6_full> is never used
Input <FX2_MONI.flag_ep6_almost> is never used
Input <FX2_MONI.flag_ep8_full> is never used
Input <FX2_MONI.flag_ep8_almost> is never used
Input <FX2_MONI.fifo_ep4> is never used
Input <FX2_MONI.fifo_ep6> is never used
Input <FX2_MONI.fifo_ep8> is never used
Output <FX2_TX2DATA> is never assigned
Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <RB_LAM_TEST<1:0>> is assigned but never used
Signal <SER_MONI.rxovr> is assigned but never used
Signal <SER_MONI.rxerr> is assigned but never used
Signal <SER_MONI.abdone> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <FX2_FLAG_N<3>> is assigned but never used
Signal <FX2_TXAFULL> is assigned but never used
Signal <FX2_RXAEMPTY> is assigned but never used
Signal <FX2_TX2ENA> is assigned but never used
Signal <FX2_TX2DATA> is assigned but never used
Signal <TXSIZE_FX2> is assigned but never used
Signal <FX2_TX2ENA_L> is used but never assigned
Signal <RESET> is used but never assigned
Signal <FX2_TX2BUSY> is used but never assigned
Signal <FX2_TX2AFULL> is never used or assigned
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <R_REGS.ucnt_6> has a constant value of 0
FF/Latch <HIO/R_REGS.ledin_[2-6]> has a constant value of 0
FF/Latch <R_REGS.rxpipe> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].rst[rw]> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].rst[rw]_(c|s|sc|ss)> has a constant value of 0
Node <HIO/R_REGS.swieff_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.swi_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-3]> of sequential type is unconnected
Node <HIO/R_REGS.btneff_[0-3]> of sequential type is unconnected
Node <TST/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.moneop> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monlamp> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monattn> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_MONI_S..*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_MONI_C..*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS..*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].size[rw]_[0-4]> of sequential type is unconnected
#
# ----------------------------------------------------------------------------
[tra]
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Signal I_FX2_FLAG<3> connected to top level port I_FX2_FLAG<3> has been removed
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete

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## $Id: sys_tst_rlink_cuff_ic_n2.ucf_cpp 466 2012-12-30 13:26:55Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2012-12-29 466 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
#include "bplib/nexys2/nexys2_pins.ucf"
##
## Pmod B0 - RS232
##
#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
##
## Cypress FX2
##
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"

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# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_rlink_cuff_n2.vbom
@ucf_cpp: sys_tst_rlink_cuff_ic_n2.ucf
@top: sys_tst_rlink_cuff_n2

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# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./as/sys_tst_rlink_cuff_as_n2
# ./ic/sys_tst_rlink_cuff_ic_n2
# ./ic3/sys_tst_rlink_cuff_ic3_n2
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../vlib/rbus/rblib.vhd
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../tst_rlink_cuff.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_rlink_cuff_n2.vhd
## no @ucf_cpp

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-- $Id: sys_tst_rlink_cuff_n2.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_n2 - syn
-- Description: rlink tester design for nexys2 with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 808 1739 160 1172 p 16.3 as2/ 50
-- 2013-01-02 467 13.3 O76d xc3s1200e-4 843 1792 160 1209 p 15.2 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 863 1850 192 1266 p 13.6 ic3/ 50
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_fx2loop_n2
-- the now obsoleted sys_tst_rlink_n2_cuff design
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_n2 is -- top level
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_n2;
architecture syn of sys_tst_rlink_cuff_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;

17
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# libs
../../vlib/slvtypes.vhd
../../vlib/genlib/genlib.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serport.vhd
../../bplib/fx2lib/fx2lib.vhd
${sys_conf := nexys2/as/sys_conf.vhd}
# components
../../vlib/rlink/rlink_core8.vbom
../../vlib/rlink/rlink_rlbmux.vbom
../../vlib/serport/serport_1clock.vbom
../tst_rlink/rbd_tst_rlink.vbom
../../vlib/rbus/rb_sres_or_2.vbom
../../vlib/genlib/led_pulse_stretch.vbom
# design
tst_rlink_cuff.vhd

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-- $Id: tst_rlink_cuff.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_rlink_cuff - syn
-- Description: tester for rlink over cuff
--
-- Dependencies: vlib/rlink/rlink_core8
-- vlib/rlink/rlink_rlbmux
-- vlib/serport/serport_1clock
-- ../tst_rlink/rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/genlib/led_pulse_stretch
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-02 467 1.0.1 use 64 usec led pulse width
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serport.all;
use work.fx2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity tst_rlink_cuff is -- tester for rlink over cuff
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RB_MREQ_TOP : out rb_mreq_type; -- rbus: request
RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level
SWI : in slv8; -- hio: switches
BTN : in slv4; -- hio: buttons
LED : out slv8; -- hio: leds
DSP_DAT : out slv16; -- hio: display data
DSP_DP : out slv4; -- hio: display decimal points
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RTS_N : out slbit; -- receive rts (uart view, act.low)
CTS_N : in slbit; -- transmit cts (uart view, act.low)
FX2_RXDATA : in slv8; -- fx2: receiver data out
FX2_RXVAL : in slbit; -- fx2: receiver data valid
FX2_RXHOLD : out slbit; -- fx2: receiver data hold
FX2_TXDATA : out slv8; -- fx2: transmit data in
FX2_TXENA : out slbit; -- fx2: transmit data enable
FX2_TXBUSY : in slbit; -- fx2: transmit busy
FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in
FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable
FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy
FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor
);
end tst_rlink_cuff;
architecture syn of tst_rlink_cuff is
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_TX2ENA_L : slbit := '0';
signal FX2_TXENA_L : slbit := '0';
signal FX2_TX2ENA_LED : slbit := '0';
signal FX2_TXENA_LED : slbit := '0';
signal FX2_RXVAL_LED : slbit := '0';
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
begin
RLCORE : rlink_core8
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon)
port map (
CLK => CLK,
CE_INT => CE_MSEC,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RLBMUX : rlink_rlbmux
port map (
SEL => SWI(2),
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA_L,
P1_TXBUSY => FX2_TXBUSY
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXSD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_TOP,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
TX2ENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TX2ENA_L,
POUT => FX2_TX2ENA_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TXENA_L,
POUT => FX2_TXENA_LED
);
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_RXVAL,
POUT => FX2_RXVAL_LED
);
proc_clkdiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_clkdiv;
proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY,
FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED)
begin
DSP_DAT <= SER_MONI.abclkdiv;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
if SWI(2) = '0' then
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
else
DSP_DP(3) <= FX2_TX2BUSY;
DSP_DP(2) <= FX2_TX2ENA_LED;
DSP_DP(1) <= FX2_TXENA_LED;
DSP_DP(0) <= FX2_RXVAL_LED;
end if;
end process proc_hiomux;
RB_MREQ_TOP <= RB_MREQ;
FX2_TX2ENA <= FX2_TX2ENA_L;
FX2_TXENA <= FX2_TXENA_L;
end syn;

5
rtl/sys_gen/tst_serloop/nexys2/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -15,8 +15,7 @@ ISE_PATH = xc3s1200e-fg320-4
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_serloop1_n2.ucf
rm -f sys_tst_serloop2_n2.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#

2
rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vbom
View File

@@ -5,7 +5,7 @@
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf1.vhd
${sys_conf := sys_conf1.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom

7
rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: sys_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -34,7 +34,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-16 439 0.5 Initial version
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
--
@@ -57,7 +58,6 @@ entity sys_tst_serloop1_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
@@ -117,7 +117,6 @@ architecture syn of sys_tst_serloop1_n2 is
begin
CLK <= I_CLK50;
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (

2
rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom
View File

@@ -6,7 +6,7 @@
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf2.vhd
${sys_conf := sys_conf2.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom

6
rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: sys_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -37,6 +37,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-09 437 1.0.4 rename serport stat->moni port
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
@@ -65,7 +66,6 @@ entity sys_tst_serloop2_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
@@ -138,8 +138,6 @@ begin
LOCKED => open
);
O_CLKSYS <= '0';
CLKDIV_U : clkdivce
generic map (
CDUWIDTH => 7,

8
rtl/sys_gen/tst_serloop/nexys2/tb/Makefile
View File

@@ -1,10 +1,14 @@
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-13 424 1.0 Initial version
#
EXE_all = tb_tst_serloop1_n2 tb_tst_serloop2_n2
EXE_all = tb_tst_serloop1_n2
EXE_all += tb_tst_serloop2_n2
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all all_ssim all_tsim clean
#

5
rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -25,6 +25,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
@@ -78,14 +79,12 @@ begin
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
UUT : entity work.sys_tst_serloop1_n2
port map (
I_CLK50 => CLK50,
O_CLKSYS => open,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,

5
rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,6 +26,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-13 424 1.0 Initial version
@@ -84,7 +85,6 @@ begin
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
@@ -113,7 +113,6 @@ begin
UUT : entity work.sys_tst_serloop2_n2
port map (
I_CLK50 => CLK50,
O_CLKSYS => open,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,

5
rtl/sys_gen/tst_serloop/nexys3/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -18,8 +18,7 @@ XFLOWOPT_IMP = imp_s6_speed.opt
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_serloop1_n3.ucf
rm -f sys_tst_serloop2_n3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#

2
rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vbom
View File

@@ -6,7 +6,7 @@
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf1.vhd
${sys_conf := sys_conf1.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom

8
rtl/sys_gen/tst_serloop/nexys3/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -7,6 +7,12 @@
#
EXE_all = tb_tst_serloop1_n3
#
ISE_BOARD = nexys3
ISE_PATH = xc6slx16-csg324-2
#
XFLOWOPT_SYN = syn_s6_speed.opt
XFLOWOPT_IMP = imp_s6_speed.opt
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)

4
rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_tst_serloop1_n3.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop1_n3.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -25,6 +25,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk
-- 2011-12-11 438 1.0 Initial version
------------------------------------------------------------------------------
@@ -77,7 +78,6 @@ begin
OFFSET => clock_offset)
port map (
CLK => CLK100,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);

4
rtl/sys_gen/tst_serloop/s3board/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -15,7 +15,7 @@ ISE_PATH = xc3s1000-ft256-4
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_serloop_s3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#

2
rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom
View File

@@ -6,7 +6,7 @@
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/s3board/s3boardlib.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom

4
rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_tst_serloop_s3.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop_s3.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,6 +26,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
------------------------------------------------------------------------------
@@ -82,7 +83,6 @@ begin
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);

1
rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom
View File

@@ -3,6 +3,7 @@
../../../vlib/simlib/simlib.vhd
../../../vlib/serport/serport.vhd
# components
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_xontx.vbom
# design

15
rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,7 +15,8 @@
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/serport/serport_uart_rxtx
-- Dependencies: vlib/simlib/simclkcnt
-- vlib/serport/serport_uart_rxtx
-- vlib/serport/serport_xontx
--
-- To test: sys_tst_serloop_xx
@@ -24,6 +25,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclkcnt
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
@@ -59,7 +61,7 @@ end tb_tst_serloop;
architecture sim of tb_tst_serloop is
signal CLK_STOP_L : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
@@ -101,12 +103,7 @@ architecture sim of tb_tst_serloop is
begin
proc_cycle: process (CLKS)
begin
if rising_edge(CLKS) then
CLK_CYCLE <= slv(unsigned(CLK_CYCLE) + 1);
end if;
end process proc_cycle;
CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE);
UART : serport_uart_rxtx
generic map (

4
rtl/sys_gen/tst_snhumanio/atlys/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 414 2011-10-11 19:38:12Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -18,7 +18,7 @@ XFLOWOPT_IMP = imp_s6_speed.opt
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_atlys.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#

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