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add w11a system for Arty with MIG

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wfjm 2019-01-04 09:19:00 +01:00
parent cb7b906089
commit dd7cdfeceb
17 changed files with 1002 additions and 10 deletions
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2
.travis.yml
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@ -17,7 +17,7 @@ matrix:
packages: g++-7
env: MATRIX_EVAL="CC=gcc-7 && CXX=g++-7"
- name: "Ub 16.04 -- clang 5.0.0"
- name: "Ub 16.04 -- clang 7.0.0"
dist: xenial
env: MATRIX_EVAL="CC=clang && CXX=clang++"

6
Makefile
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@ -1,4 +1,4 @@
# $Id: Makefile 1101 2019-01-02 21:22:37Z mueller $
# $Id: Makefile 1102 2019-01-03 08:46:04Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@ -6,7 +6,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2019-01-02 1101 1.2.10 add tst_{mig,sram}/arty
# 2019-01-02 1101 1.2.10 add tst_{mig,sram}/arty; add w11a/arty
# 2018-10-12 1055 1.2.9 use setup_package_filt
# 2017-06-28 918 1.2.8 add cmoda7 port for tst_rlink,tst_sram,w11a
# 2017-05-01 891 1.2.7 add all_tcl to all; use njobihtm
@ -78,6 +78,7 @@ SYN_viv += rtl/sys_gen/w11a/nexys4
SYN_viv += rtl/sys_gen/tst_mig/arty
SYN_viv += rtl/sys_gen/tst_rlink/arty
SYN_viv += rtl/sys_gen/tst_sram/arty
SYN_viv += rtl/sys_gen/w11a/arty
SYN_viv += rtl/sys_gen/w11a/arty_bram
# CmodA7 -------------------------------------
@ -137,6 +138,7 @@ SIM_viv += rtl/sys_gen/w11a/nexys4/tb
SIM_viv += rtl/sys_gen/tst_mig/arty/tb
SIM_viv += rtl/sys_gen/tst_rlink/arty/tb
SIM_viv += rtl/sys_gen/tst_sram/arty/tb
SIM_viv += rtl/sys_gen/w11a/arty/tb
SIM_viv += rtl/sys_gen/w11a/arty_bram/tb
# CmodA7 -------------------------------------

2
doc/CHANGELOG.md
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@ -23,11 +23,13 @@ The full set of tests is only run for tagged releases.
### Summary
- add support DDR memory via Vivado MIG cores
- arty board support
- add w11a, tst_sram and tst_mig systems
### New features
- new systems
- sys_tst_mig_arty: low level MIG interface test
- sys_tst_sram_arty: memory test
- sys_w11a_arty: w11a with full 3840 MB memory
- new components
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk

25
rtl/sys_gen/w11a/arty/Makefile Normal file
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@ -0,0 +1,25 @@
# $Id: Makefile 1071 2018-11-17 20:53:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-11-17 1071 1.0 Initial version
#
VBOM_all = sys_w11a_arty.vbom
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : viv_clean
#
#----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#

93
rtl/sys_gen/w11a/arty/sys_conf.vhd Normal file
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@ -0,0 +1,93 @@
-- $Id: sys_conf.vhd 1072 2018-11-18 22:27:35Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_arty (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version (derived from _br_arty version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11
constant sys_conf_ibd_pc11 : boolean := true; -- PC11
constant sys_conf_ibd_lp11 : boolean := true; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

35
rtl/sys_gen/w11a/arty/sys_w11a_arty.vbom Normal file
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@ -0,0 +1,35 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/cdclib/cdclib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rbus/rbdlib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/sysmon/sysmonrbuslib.vbom
../../../bplib/mig/miglib.vbom
../../../bplib/arty/miglib_arty.vbom
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vhd}
@lib:unisim
# components
../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom
../../../vlib/cdclib/cdc_signal_s1_as.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom
../../../w11a/pdp11_sys70.vbom
../../../ibus/ibdr_maxisys.vbom
../../../bplib/arty/sramif_mig_arty.vbom
../../../vlib/rlink/ioleds_sp1c.vbom
../arty_bram/pdp11_hio70_arty.vbom
../../../bplib/bpgen/bp_swibtnled.vbom
../../../bplib/bpgen/rgbdrv_3x4mux.vbom
../../../bplib/sysmon/sysmonx_rbus_arty.vbom
../../../vlib/rbus/rbd_usracc.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
# design
sys_w11a_arty.vhd
@xdc:../../../bplib/arty/arty_pclk.xdc
@xdc:../../../bplib/arty/arty_pins.xdc

516
rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd Normal file
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@ -0,0 +1,516 @@
-- $Id: sys_w11a_arty.vhd 1101 2019-01-02 21:22:37Z mueller $
--
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_arty - syn
-- Description: w11a test design for arty (with dram via mig)
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/arty/sramif_mig_arty
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_arty
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x4mux
-- bplib/sysmon/sysmonx_rbus_arty
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_arty
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-01-02 1101 2017.2 xc7a35t-1l 6575 10610 820 17.0 3144
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-28 1096 1.1.1 setup reset for sramif_mig_arty
-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce2c
-- 2018-11-18 1072 1.0 Initial version
-- 2018-11-17 1071 0.1 First draft (derived from sys_w11a_br_arty)
------------------------------------------------------------------------------
--
-- w11a design for arty (using DDR3 memory via MIG)
-- w11a + rlink + serport
--
-- Usage of Arty switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows upper, RGB low nibble of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (3) kernel mode, non-wait, pri>0
-- (2) kernel mode, non-wait, pri=0
-- (1) supervisor mode
-- (0) user mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (3:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (3) MEM_ACT_W
-- (2) MEM_ACT_R
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR(11:08)
-- RGB_G DR( 7:04)
-- RGB_R DR( 3:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_arty.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
library unisim;
use unisim.vcomponents.ALL;
-- ----------------------------------------------------------------------------
entity sys_w11a_arty is -- top level
-- implements arty_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_w11a_arty;
architecture syn of sys_w11a_arty is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv4 := (others=>'0');
signal RGB_G : slv4 := (others=>'0');
signal RGB_B : slv4 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
CLK100_BUFG: bufg
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 10, -- vco 1000 MHz
CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 9, -- 512 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEMCTL: sramif_mig_arty -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => GBL_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLKMIG,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x4mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3
);
SMRB: sysmonx_rbus_arty -- always instantiated, needed for mig
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;

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# $Id: sys_w11a_arty.vmfset 1101 2019-01-02 21:22:37Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# binding instance .. which has no pins ------------------------
I [Synth 8-115] # generic
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
# net without driver -------------------------------------------
# unconnected ports --------------------------------------------
I [Synth 8-3331] IB_MREQ # generic
I [Synth 8-3331] RB_MREQ # generic
I [Synth 8-3331] DM_STAT_CO # generic
I [Synth 8-3331] DM_STAT_DP # generic
I [Synth 8-3331] DM_STAT_EXP # generic
I [Synth 8-3331] DM_STAT_SE # generic
I [Synth 8-3331] DM_STAT_VM # generic
I [Synth 8-3331] CP_STAT # generic
I [Synth 8-3331] SER_MONI # generic
# --> ireg indeed not fully used # OK 2018-12-28
i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)]
# --> ccin indedd not fully used # OK 2018-12-28
i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are used # OK 2018-12-28
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-12-28
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-12-28
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-12-28
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
# --> msec indeed not used # OK 2018-12-28
i [Synth 8-3331] ibdr_rl11 .* CE_MSEC
# --> ei_ack not used, interrupt request cleared via register # OK 2018-12-28
i [Synth 8-3331] ibdr_deuna .* EI_ACK
i [Synth 8-3331] ibd_iist .* EI_ACK
# --> data end marker not used # OK 2019-01-02
i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2018-12-28
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[usec]
# --> indeed no types with [3] set # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> monitor outputs moneop,monattn currently not used # OK 2018-12-28
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-12-28
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> not yet used # OK 2018-12-28
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> [8] is for DZ11TX, not yet available # OK 2018-12-28
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-12-28
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
{:}
# INFO: encoded FSM with state register as --------------------
# test for sys_w11a_br_arty that all FSMs are one_hot
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox'
r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core'
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps
I [Physopt 32-742] # BRAM Flop Optimization
{:2017.2}
# --> spurious Invalid VCCINTIO messages # OK 2018-12-28
i [Designutils 20-266] Invalid Voltage Source VCCINTIO
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[bit]
# see https://www.xilinx.com/support/answers/64180.html # OK 2018-12-28
i [DRC REQP-1709] PLLE2_ADV
# --> DSP multiplier is not pipelined, ok # OK 2018-12-28
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining

2
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tb_w11a_arty
sysmon_stim

39
rtl/sys_gen/w11a/arty/tb/Makefile Normal file
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# $Id: Makefile 1071 2018-11-17 20:53:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-11-17 1071 1.0 Initial version
#
EXE_all = tb_w11a_arty
#
include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
include $(wildcard *.o.dep_ghdl)
endif
#

90
rtl/sys_gen/w11a/arty/tb/sys_conf_sim.vhd Normal file
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-- $Id: sys_conf_sim.vhd 1072 2018-11-18 22:27:35Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_arty (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version (derived from _br_arty version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11
constant sys_conf_ibd_pc11 : boolean := true; -- PC11
constant sys_conf_ibd_lp11 : boolean := true; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;

9
rtl/sys_gen/w11a/arty/tb/tb_w11a_arty.vbom Normal file
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# configure tb_arty_dram with sys_w11a_arty target;
# use vhdl configure file (tb_w11a_arty.vhd) to allow
# that all configurations will co-exist in work library
# configure
arty_dram_aif = ../sys_w11a_arty.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/arty/tb/tb_arty_dram.vbom
tb_w11a_arty.vhd

35
rtl/sys_gen/w11a/arty/tb/tb_w11a_arty.vhd Normal file
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-- $Id: tb_w11a_arty.vhd 1071 2018-11-17 20:53:26Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_arty
-- Description: Configuration for tb_w11a_arty for tb_arty_dram
--
-- Dependencies: sys_w11a_arty
--
-- To test: sys_w11a_arty
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_w11a_arty of tb_arty_dram is
for sim
for all : arty_dram_aif
use entity work.sys_w11a_arty;
end for;
end for;
end tb_w11a_arty;

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# $Id: tbrun.yml 1071 2018-11-17 20:53:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-11-17 1071 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, sys_w11a, arty, stim1]
test: |
tbrun_tbwrri --hxon --lsuf stim1 tb_w11a_arty${ms} \
"rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat"
- tag: [default, viv, sys_w11a, arty, stim2]
test: |
tbrun_tbwrri --hxon --lsuf stim2 --pack rw11 tb_w11a_arty${ms} \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60."
- tag: [default, viv, sys_w11a, arty, tbcpu]
test: |
tbrun_tbwrri --hxon --lsuf tbcpu --pack rw11 tb_w11a_arty${ms} \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
- tag: [default, viv, sys_w11a, arty, tbdev]
test: |
tbrun_tbwrri --hxon --lsuf tbdev --pack rw11 tb_w11a_arty${ms} \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"

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# $Id: tbw.dat 1071 2018-11-17 20:53:26Z mueller $
#
[tb_w11a_arty]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_arty.dat

6
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to_ptp
to_lda
*.lda
lpt.dat
ptp.dat
*.LOG

4
rtl/sys_gen/w11a/tbrun.yml
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@ -1,7 +1,8 @@
# $Id: tbrun.yml 1038 2018-08-11 12:39:52Z mueller $
# $Id: tbrun.yml 1102 2019-01-03 08:46:04Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2019-01-03 1102 1.2 add arty(dram)
# 2018-08-11 1038 1.1 add artys7
# 2017-06-25 914 1.1 add cmoda7
# 2016-08-22 800 1.0 Initial version
@ -11,6 +12,7 @@
- include: nexys3/tb/tbrun.yml
- include: nexys4/tb/tbrun.yml
- include: basys3/tb/tbrun.yml
- include: arty/tb/tbrun.yml
- include: arty_bram/tb/tbrun.yml
- include: artys7_bram/tb/tbrun.yml
- include: cmoda7/tb/tbrun.yml