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add w11a system for Arty with MIG

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wfjm
2019-01-04 09:19:00 +01:00
parent cb7b906089
commit dd7cdfeceb
17 changed files with 1002 additions and 10 deletions
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Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 1101 2019-01-02 21:22:37Z mueller $
# $Id: Makefile 1102 2019-01-03 08:46:04Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -6,7 +6,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2019-01-02 1101 1.2.10 add tst_{mig,sram}/arty
# 2019-01-02 1101 1.2.10 add tst_{mig,sram}/arty; add w11a/arty
# 2018-10-12 1055 1.2.9 use setup_package_filt
# 2017-06-28 918 1.2.8 add cmoda7 port for tst_rlink,tst_sram,w11a
# 2017-05-01 891 1.2.7 add all_tcl to all; use njobihtm
@@ -78,6 +78,7 @@ SYN_viv += rtl/sys_gen/w11a/nexys4
SYN_viv += rtl/sys_gen/tst_mig/arty
SYN_viv += rtl/sys_gen/tst_rlink/arty
SYN_viv += rtl/sys_gen/tst_sram/arty
SYN_viv += rtl/sys_gen/w11a/arty
SYN_viv += rtl/sys_gen/w11a/arty_bram
# CmodA7 -------------------------------------
@@ -137,6 +138,7 @@ SIM_viv += rtl/sys_gen/w11a/nexys4/tb
SIM_viv += rtl/sys_gen/tst_mig/arty/tb
SIM_viv += rtl/sys_gen/tst_rlink/arty/tb
SIM_viv += rtl/sys_gen/tst_sram/arty/tb
SIM_viv += rtl/sys_gen/w11a/arty/tb
SIM_viv += rtl/sys_gen/w11a/arty_bram/tb
# CmodA7 -------------------------------------