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tcode cpu_details.mac: add B*: Stress tests
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wfjm
@@ -1,4 +1,4 @@
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; $Id: cpu_details.mac 1259 2022-07-18 17:39:40Z mueller $
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; $Id: cpu_details.mac 1261 2022-07-23 16:15:03Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -7,19 +7,18 @@
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; 2022-07-18 1259 1.0 Initial version
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;
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; Test CPU details
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; Section A: CPUERR
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; Section B: PIRQ
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; Section C: stress tests
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; Section D: 11/70 specifics
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; Section A: CPU registers
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; Section B: stress tests
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; Section C: 11/70 specifics
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;
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.include |lib/tcode_std_base.mac|
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;
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; Section B: PIRQ ============================================================
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; Section A: CPU registers ===================================================
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;
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; Test B1: PIRQ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Test A1: PIRQ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies operation of PIRQ register
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;
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; Test B1.1 -- PIRQ + spl ++++++++++++++++++++++++++++++++++++++++++++
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; Test A1.1 -- PIRQ + spl ++++++++++++++++++++++++++++++++++++++++++++
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; This test will exercise all 7 pirq interrupt levels:
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; set 1+3 -> handle 3, set 7
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; -> handle 7, set 6+4
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@@ -47,7 +46,7 @@
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pi.n06=6*042 ; lsb for pir 6 next
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pi.n07=7*042 ; lsb for pir 7 next
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;
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tb0101: mov #1000$,v..pir ; setup handler
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ta0101: mov #1000$,v..pir ; setup handler
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mov #cp.pr7,v..pir+2 ; which runs at pr7
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mov #cp.pir,r3 ; ptr to PIRQ
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mov #cp.psw,r4 ; ptr to PSW
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@@ -56,11 +55,11 @@ tb0101: mov #1000$,v..pir ; setup handler
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;
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spl 7 ; lockout interrupts
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bisb #bit01,1(r3) ; set PIRQ 1
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cmp (r3),#<pi.r01+pi.n01> ; check set 1
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cmp (r3),#<pi.r01!pi.n01> ; check set 1
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beq .+4
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halt
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bisb #bit03,1(r3) ; set PIRQ 3
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cmp (r3),#<pi.r01+pi.r03+pi.n03> ; check set 1+3
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cmp (r3),#<pi.r01!pi.r03!pi.n03> ; check set 1+3
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beq .+4
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halt
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spl 2
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@@ -106,28 +105,208 @@ tb0101: mov #1000$,v..pir ; setup handler
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.word 0 ; new pirq @ level 1
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.word 0 ; new pirq @ level 2
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.word pi.r07 ; new pirq @ level 3 -> 7
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.word pi.r05+pi.r02 ; new pirq @ level 4 -> 5+2
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.word pi.r05!pi.r02 ; new pirq @ level 4 -> 5+2
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.word 0 ; new pirq @ level 5
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.word 0 ; new pirq @ level 6
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.word pi.r06+pi.r04 ; new pirq @ level 7 -> 6+4
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.word pi.r06!pi.r04 ; new pirq @ level 7 -> 6+4
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;
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; table with expected values of pirq register in interrupt sequence
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1200$: .word 1,pi.r01+pi.r03+pi.n03 ; set 1+3 -> handle 3, set 7
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.word 2,pi.r01+pi.r07+pi.n07 ; set 1+7 -> handle 7, set 6+4
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.word 2,pi.r01+pi.r04+pi.r06+pi.n06 ; set 1+4+6 -> handle 6
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.word 2,pi.r01+pi.r04+pi.n04 ; set 1+4 -> handle 4, set 5+2
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.word 3,pi.r01+pi.r02+pi.r05+pi.n05 ; set 1+2+5 -> handle 5
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.word 1,pi.r01+pi.r02+pi.n02 ; set 1+2 -> handle 2
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.word 1,pi.r01+pi.n01 ; set 1 -> handle 1
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1200$: .word 1,pi.r01!pi.r03!pi.n03 ; set 1+3 -> handle 3, set 7
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.word 2,pi.r01!pi.r07!pi.n07 ; set 1+7 -> handle 7, set 6+4
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.word 2,pi.r01!pi.r04!pi.r06!pi.n06 ; set 1+4+6 -> handle 6
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.word 2,pi.r01!pi.r04!pi.n04 ; set 1+4 -> handle 4, set 5+2
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.word 3,pi.r01!pi.r02!pi.r05!pi.n05 ; set 1+2+5 -> handle 5
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.word 1,pi.r01!pi.r02!pi.n02 ; set 1+2 -> handle 2
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.word 1,pi.r01!pi.n01 ; set 1 -> handle 1
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; nesting level counter
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1300$: .word 0
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;
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9999$: iot ; end of test A1.1
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;
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; Section B: Stress tests ====================================================
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;
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; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
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; This sub-section tests peculiar address node usage
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;
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; Test B1.1 -- src-dst update hazards with (r0)+,(r0) ++++++++++++++++
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;
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tb0101: mov #2,r5
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100$: mov #1000$,r0
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mov #1110$,r1
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mov 1000$+2,-(sp) ; save data that will change
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mov 1000$+6,-(sp)
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mov 1100$+0,-(sp)
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mov 1100$+4,-(sp)
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;
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mov (r0)+,(r0)+ ; mov 111 over 222
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add (r0)+,(r0)+ ; add 333 to 444
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mov -(r1),-(r1) ; mov 444 over 333
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add -(r1),-(r1) ; add 222 to 111
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;
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cmp 1000$+2,#000111
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beq .+4
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halt
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cmp 1000$+6,#000777
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beq .+4
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halt
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cmp 1100$+4,#000444
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beq .+4
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halt
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cmp 1100$+0,#000333
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beq .+4
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halt
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;
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mov (sp)+,1100$+4 ; restore data
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mov (sp)+,1100$+0
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mov (sp)+,1000$+6
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mov (sp)+,1000$+2
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sob r5,100$
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jmp 9999$
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;
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1000$: .word 000111 ; data for (r0)+ part
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.word 000222
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.word 000333
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.word 000444
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;
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1100$: .word 000111 ; data for -(r0) part
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.word 000222
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.word 000333
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.word 000444
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1110$:
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;
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9999$: iot ; end of test B1.1
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;
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; Test B1.2 -- (pc)+ as destination ++++++++++++++++++++++++++++++++++
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;
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tb0102: mov #2,r5
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100$: mov 1000$+4,-(sp) ; save data that will change
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mov 1100$+4,-(sp)
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mov 1200$+2,-(sp)
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;
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clr r0
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1000$: mov #1,#0 ; (pc)+,(pc)+: write #1 over #0
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1100$: add #1,#2 ; (pc)+,(pc)+: add #1 to #2
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mov 1000$+4,1200$+2 ; -14(pc),2(pc): dst of mov -> src of add
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1200$: add #0,r0 ; add #1(!) to r0
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;
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cmp 1000$+4,#1
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beq .+4
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halt
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cmp 1100$+4,#3
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beq .+4
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halt
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cmp r0,#1
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beq .+4
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halt
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;
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mov (sp)+,1200$+2 ; restore data
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mov (sp)+,1100$+4
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mov (sp)+,1000$+4
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sob r5,100$
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;
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9999$: iot ; end of test B1.2
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;
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; Test B1.3 -- pc as destination in clr, mov, and add ++++++++++++++++
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;
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tb0103: mov #000137,@#0 ; setup jmp 1000$ at mem(0)
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mov #1000$,@#2
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clr pc
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halt
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halt
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halt
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1000$: mov #1100$,pc
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halt
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halt
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halt
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1100$: clr r0
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add #4,pc ; skip two instructions
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inc r0
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inc r0
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inc r0 ; lands here
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inc r0
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cmp r0,#2
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beq .+4
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halt
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;
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clr @#0 ; remove jmp 1000$ at mem(0)
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clr @#2
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;
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9999$: iot ; end of test B1.3
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;
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; Test B2: pipeline torture tests +++++++++++++++++++++++++++++++++++++++++++
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; This sub-section tests self-modifying code
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;
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; Test B2.1 -- self-modifying code, use (pc), -(pc) ++++++++++++++++++
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;
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tb0201: mov #2,r5
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100$: mov 1000$,-(sp)
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mov 1100$,-(sp)
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;
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clr r0
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clr r1
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clr r2
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mov #005201,r3 ; r3= inc r1
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mov #005202,r4 ; r4= inc r2
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;
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inc r0
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mov r3,(pc) ; will overwrite next instruction
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1000$: halt ; will be overwritten with 'inc r1'
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inc r0
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1100$: mov r4,-(pc) ; will overwrite itself and re-execute(!)
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inc r0
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;
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cmp r0,#3 ; 3 inc r0 in code
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beq .+4
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halt
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cmp r1,#1 ; check that 'inc r1' was executed
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beq .+4
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halt
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cmp r2,#1 ; check that 'inc r2' was executed
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beq .+4
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halt
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;
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mov (sp)+,1100$
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mov (sp)+,1000$
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sob r5,100$
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;
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9999$: iot ; end of test B2.1
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;
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; Test B2.2 -- self-modifying code, use (pc) case 2 ++++++++++++++++++
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; Was insprired by KDJ11A.MAC (J11 is indeed pipelined)
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;
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tb0202: mov #2,r5
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100$: mov 1000$,-(sp)
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mov 1100$,-(sp)
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mov 1200$,-(sp)
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;
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mov #1999$,r1
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clr r2
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;
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mov #005202,(pc) ; will replace jmp (r1) with 'inc r2'
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1000$: jmp (r1)
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mov #005202,(pc) ; will replace jmp (r1) with 'inc r2'
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1100$: jmp (r1)
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mov #005202,(pc) ; will replace jmp (r1) with 'inc r2'
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1200$: jmp (r1)
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;
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cmp r2,#3 ; check that 'inc r2' was executed
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beq .+4
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halt
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;
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mov (sp)+,1200$
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mov (sp)+,1100$
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mov (sp)+,1000$
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sob r5,100$
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jmp 9999$
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;
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1999$: halt ; halt as target for 'jmp (r1)'
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;
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9999$: iot ; end of test B2.2
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;
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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cmp tstno,#1. ; all tests done ?
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cmp tstno,#6. ; all tests done ?
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beq .+4
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halt
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;
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