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tcode cpu_basics.mac: add F3: trap instructions
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@ -1,4 +1,4 @@
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; $Id: cpu_basics.mac 1259 2022-07-18 17:39:40Z mueller $
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; $Id: cpu_basics.mac 1261 2022-07-23 16:15:03Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@ -13,7 +13,7 @@
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; Section C: binary instructions (word)
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; Section D: unary instructions (byte)
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; Section E: binary instructions (byte)
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; Section F: miscellaneous (spl, reset)
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; Section F: miscellaneous (spl, reset, bpt,...)
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;
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.include |lib/tcode_std_base.mac|
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.include |lib/defs_kwl.mac|
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@ -1043,7 +1043,7 @@ ta0501: mov #123456,r5 ; token
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mov #101,-(sp) ; push 1st parameter
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mov #102,-(sp) ; push 2nd parameter
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mov #103,-(sp) ; push 3rd parameter
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mov #<mark+3>,-(sp) ; push MARK 3
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mov #<mark!3>,-(sp) ; push MARK 3
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mov sp,r5 ; push address of MARK 3
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jsr pc,100$ ; call procedure
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cmp r5,#123456 ; check token
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@ -3007,56 +3007,56 @@ tf0101: mov #cp.psw,r0
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ccc
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sen
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spl 1
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cmp (r0),#<cp.pr1+cpn000>
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cmp (r0),#<cp.pr1!cpn000>
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beq .+4
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halt
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;
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ccc
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sez
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spl 2
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cmp (r0),#<cp.pr2+cp0z00>
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cmp (r0),#<cp.pr2!cp0z00>
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beq .+4
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halt
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;
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ccc
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sev
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spl 3
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cmp (r0),#<cp.pr3+cp00v0>
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cmp (r0),#<cp.pr3!cp00v0>
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beq .+4
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halt
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;
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ccc
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sec
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spl 4
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cmp (r0),#<cp.pr4+cp000c>
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cmp (r0),#<cp.pr4!cp000c>
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beq .+4
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halt
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;
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scc
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cln
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spl 5
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cmp (r0),#<cp.pr5+cp0zvc>
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cmp (r0),#<cp.pr5!cp0zvc>
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beq .+4
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halt
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;
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scc
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clz
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spl 6
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cmp (r0),#<cp.pr6+cpn0vc>
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cmp (r0),#<cp.pr6!cpn0vc>
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beq .+4
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halt
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;
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scc
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clv
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spl 7
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cmp (r0),#<cp.pr7+cpnz0c>
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cmp (r0),#<cp.pr7!cpnz0c>
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beq .+4
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halt
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;
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scc
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clc
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spl 0
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cmp (r0),#<cp.pr0+cpnzv0>
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cmp (r0),#<cp.pr0!cpnzv0>
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beq .+4
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halt
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;
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@ -3070,14 +3070,14 @@ tf0102: mov #cp.psw,r0
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mov #cp.cms,(r0) ; to supervisor mode
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ccc
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spl 4
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cmp (r0),#<cp.cms+cp.pr0+cp0000>
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cmp (r0),#<cp.cms!cp.pr0!cp0000>
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beq .+4
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halt
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;
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mov #cp.cmu,(r0) ; to user mode
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scc
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spl 5
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cmp (r0),#<cp.cmu+cp.pr0+cpnzvc>
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cmp (r0),#<cp.cmu!cp.pr0!cpnzvc>
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beq .+4
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halt
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;
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@ -3095,7 +3095,7 @@ tf0102: mov #cp.psw,r0
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; - KW11-L line clock csr is cleared (representing all devices)
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; - PIRQ is cleared
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; - STKLIM is cleared
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; Effect on MMR0 and MMR3 is tested in MMU test
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; Effect on MMR0 and MMR3 is tested in MMU test cpu_mmu.mac
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;
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tf0201: mov #cp.psw,r0
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mov #cp.pr7,(r0) ; lock-out interrupts
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@ -3138,13 +3138,13 @@ tf0202: mov #cp.psw,r0
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mov #cp.pr7,(r0) ; lock-out interrupts
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mov #kl.ie,kl.csr ; enable KW11-L interrupt
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;
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mov #<cp.cms+cp.pr7>,(r0) ; supervisor mode, keep pr7 !
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mov #<cp.cms!cp.pr7>,(r0) ; supervisor mode, keep pr7 !
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reset ; and RESET
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bit #kl.ie,kl.csr ; check that bit is set
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bne .+4
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halt
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;
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mov #<cp.cmu+cp.pr7>,(r0) ; user mode, keep pr7 !
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mov #<cp.cmu!cp.pr7>,(r0) ; user mode, keep pr7 !
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reset ; and RESET
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bit #kl.ie,kl.csr ; check that bit is set
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bne .+4
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@ -3156,10 +3156,111 @@ tf0202: mov #cp.psw,r0
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;
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9999$: iot ; end of test F2.2
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;
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; Test F3: trap instructions: bpt,iot,emt,trap +++++++++++++++++++++++++++++++
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; This sub-section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 000 000 000 000 011 NZVC BPT
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; 0 000 000 000 000 100 NZVC IOT
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; 1 000 100 0ii iii iii NZVC EMT
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; 1 000 100 1ii iii iii NZVC TRAP
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; 0 000 000 000 000 010 NZVC RTI
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;
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; Test F3.1 trap instructions: bpt,iot,emt,trap ++++++++++++++++++++++
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;
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tf0301: mov #v..iot+2,v..iot ; block iot handler
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clr v..iot+2
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clr cp.psw ; clear psw
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mov #3000$,r5 ; setup expect buffer
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;
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; test bpt
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;
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mov #2000$,v..bpt ; setup bpt handler: nzvc = 0011
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mov #cp.pr7!cp00vc,v..bpt+2
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spl 1
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ccc
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sec
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bpt ; bpt with pr1 + nzvc = 0001
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mov #v..bpt+2,v..bpt ; block bpt again
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clr v..bpt+2
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;
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; test iot
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;
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mov #2000$,v..iot ; setup bpt handler: nzvc = 0100
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mov #cp.pr7!cp0z00,v..iot+2
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spl 2
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ccc
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sev
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iot ; iot with pr2 + nzvc = 0010
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mov #v..iot+2,v..iot ; block iot again
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clr v..iot+2
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;
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; test emt 123
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;
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mov #2000$,v..emt ; setup emt handler: nzvc = 0101
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mov #cp.pr7!cp0z0c,v..emt+2
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spl 3
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ccc
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sez
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emt 123 ; emt with pr3 + nzvc = 0100
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; test emt 234
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spl 4
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ccc
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sez
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emt 234 ; emt with pr4 + nzvc = 0100
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mov #v..emt+2,v..emt ; block emt again
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clr v..emt+2
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;
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; test trap 321
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;
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mov #2000$,v..trp ; setup trap handler: nzvc = 0110
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mov #cp.pr7!cp0zv0,v..trp+2
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spl 5
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ccc
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sen
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trap 321 ; trap with pr5 + nzvc = 1000
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; test trap 135
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spl 6
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ccc
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sen
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trap 135 ; trap with pr6 + nzvc = 1000
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mov #v..trp+2,v..trp ; block trap again
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clr v..trp+2
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;
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; end of trap instruction tests
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;
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cmp r5,#3001$
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mov #vh.iot,v..iot ; restore iot handler
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mov #cp.pr7,v..iot+2
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jmp 9999$
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;
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; vector handler (used for all trap type instructions)
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2000$: cmp cp.psw,(r5)+ ; check new psw
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beq .+4
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halt
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cmp 2(sp),(r5)+ ; check saved saved psw
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beq .+4
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halt
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mov (sp),r0 ; get return address
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cmp -2(r0),(r5)+ ; check instruction
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beq .+4
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halt
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rti
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; expect: new psw saved psw instruction
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3000$: .word cp.pr7!cp00vc, cp.pr1!cp000c, <bpt>
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.word cp.pr7!cp0z00, cp.pr2!cp00v0, <iot>
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.word cp.pr7!cp0z0c, cp.pr3!cp0z00, <emt!123>
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.word cp.pr7!cp0z0c, cp.pr4!cp0z00, <emt!234>
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.word cp.pr7!cp0zv0, cp.pr5!cpn000, <trap!321>
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.word cp.pr7!cp0zv0, cp.pr6!cpn000, <trap!135>
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3001$:
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;
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9999$: iot ; end of test F3.1
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;
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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cmp tstno,#51. ; all tests done ?
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cmp tstno,#52. ; all tests done ?
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beq .+4
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halt
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;
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