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Code Issues Releases Wiki Activity

drop DM_STAT_SY, add DM_STAT_CA and cache monitoring

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This commit is contained in:
wfjm
2018-10-07 08:48:24 +02:00
parent 102845ccf6
commit f40108cb95
14 changed files with 579 additions and 131 deletions
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34
tools/bin/tmuconv
View File

@@ -1,7 +1,7 @@
#!/usr/bin/perl -w
# $Id: tmuconv 985 2018-01-03 08:59:40Z mueller $
# $Id: tmuconv 1053 2018-10-06 20:34:52Z mueller $
#
# Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -14,6 +14,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2018-10-05 1053 1.1.2 use 'ca.*' instead of 'sy.*' fields
# 2015-11-01 712 1.1.1 BUGFIX: fix '.' handling for br/sob instructions
# BUGFIX: correct xor (now r,dst, and not src,r)
# br/sob offsets now octal; assume --t_id if no opts
@@ -71,7 +72,14 @@
# co.cpususp:b
# co.suspint:b
# co.suspext:b
# sy.chit:b
# ca.rd:b
# ca.wr:b
# ca.rdhit:b
# ca.wrhit:b
# ca.rdmem:b
# ca.wrmem:b
# ca.rdwait:b
# ca.wrwait:b
#
use 5.14.0; # require Perl 5.14 or higher
@@ -140,7 +148,14 @@ my $ind_vm_emsres_ack_r;
my $ind_vm_emsres_ack_w;
my $ind_vm_emsres_dout;
my $ind_sy_chit;
my $ind_ca_rd;
my $ind_ca_wr;
my $ind_ca_rdhit;
my $ind_ca_wrhit;
my $ind_ca_rdmem;
my $ind_ca_wrmem;
my $ind_ca_rdwait;
my $ind_ca_wrwait;
my @pdp11_opcode_tbl = (
{code=>0000000, mask=>0000000, name=>"halt", type=>"0arg"},
@@ -530,7 +545,14 @@ sub do_file {
$ind_vm_emsres_ack_w = $name{'vm.emsres.ack_w'}->{ind};
$ind_vm_emsres_dout = $name{'vm.emsres.dout'}->{ind};
$ind_sy_chit = $name{'sy.chit'}->{ind};
$ind_ca_rd = $name{'ca.rd'}->{ind};
$ind_ca_wr = $name{'ca.wr'}->{ind};
$ind_ca_rdhit = $name{'ca.rdhit'}->{ind};
$ind_ca_wrhit = $name{'ca.wrhit'}->{ind};
$ind_ca_rdmem = $name{'ca.rdmem'}->{ind};
$ind_ca_wrmem = $name{'ca.wrmem'}->{ind};
$ind_ca_rdwait = $name{'ca.rdwait'}->{ind};
$ind_ca_wrwait = $name{'ca.wrwait'}->{ind};
} else {
@val_last = @val_curr;
@@ -684,7 +706,7 @@ sub do_file {
$val_curr[$ind_vm_emmreq_cancel],
$val_curr[$ind_vm_emsres_ack_r],
$val_curr[$ind_vm_emsres_ack_w],
$val_curr[$ind_sy_chit];
$val_curr[$ind_ca_rdhit];
if ($val_curr[$ind_vm_emmreq_cancel]) {
$emreq_str .= " cancel";
$emcurr_we = undef;

41
tools/tbench/w11a_pcnt/test_pcnt_basics.tcl
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@@ -1,16 +1,16 @@
# $Id: test_pcnt_basics.tcl 1050 2018-09-23 15:46:42Z mueller $
# $Id: test_pcnt_basics.tcl 1053 2018-10-06 20:34:52Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2018-09-23 1450 1.0 Initial version
# 2018-09-23 1050 1.0 Initial version
#
# Test basic perf counter functionality
# ----------------------------------------------------------------------------
rlc log "test_pcnt_regs: test register response ------------------------------"
rlc log "test_pcnt_basics: test basic functionality --------------------------"
if {[$cpu get haspcnt] == 0} {
rlc log " test_pcnt_regs-W: no pcnt unit found, test aborted"
@@ -20,13 +20,13 @@ if {[$cpu get haspcnt] == 0} {
# -- Section A ---------------------------------------------------------------
rlc log " A: simple loop code ---------------------------------------"
cpu0 ldasm -lst lst -sym sym {
$cpu ldasm -lst lst -sym sym {
. = 1000
stack:
start: clr r0
mov #32.,r1
1$: inc r0
sob r1,1$
start: clr r1
mov #32.,r0
1$: inc r1
sob r0,1$
halt
stop:
}
@@ -40,7 +40,7 @@ $cpu cp \
# run code
rw11::asmrun $cpu sym
rw11::asmwait $cpu sym
rw11::asmtreg $cpu r0 32 r1 0
rw11::asmtreg $cpu r0 0 r1 32
# stop pcnt
$cpu cp \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}] \
@@ -52,11 +52,11 @@ $cpu cp \
# 4 =0 cpu_sm
# 5 =0 cpu_um
# 6 67 cpu_inst
# 7 =0 cpu_vfetch
# 8 =0 cpu_irupt
# 9 33 cpu_pcload
# 7 31 cpu_pcload
# 8 =0 cpu_vfetch
# 9 =0 cpu_irupt
rlc log " A2: test random access (ainc=0) --------------------"
# read pc(6) twice, (9) once, check status
# read pc(6) twice, (9) once, (7) one, check status
$cpu cp \
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 6 ainc 0] \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 6 ainc 0] \
@@ -70,10 +70,13 @@ $cpu cp \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 6 waddr 0 ainc 0] \
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 9 ainc 0] \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 ainc 0] \
-rreg pc.data -edata 33 \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 waddr 1 ainc 0] \
-rreg pc.data -edata 0 \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 waddr 0 ainc 0]
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 7 ainc 0] \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 ainc 0] \
-rreg pc.data -edata 31 \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 waddr 1 ainc 0] \
-rreg pc.data -edata 0 \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 waddr 0 ainc 0]
rlc log " A3: test sequential access (ainc=1) ----------------"
# read pc(6) to pc(9) check status
@@ -84,11 +87,11 @@ $cpu cp \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 6 waddr 1 ainc 1] \
-rreg pc.data -edata 0 \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 waddr 0 ainc 1] \
-rreg pc.data -edata 31 \
-rreg pc.data -edata 0 \
-rreg pc.data -edata 0 \
-rreg pc.data -edata 0 \
-rreg pc.data -edata 0 \
-rreg pc.data -edata 33 \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 waddr 1 ainc 1] \
-rreg pc.data -edata 0 \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 10 waddr 0 ainc 1]
@@ -98,7 +101,7 @@ rlc log " A3: test block access (ainc=1) ---------------------"
$cpu cp \
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 3 ainc 1] \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 3 ainc 1] \
-rblk pc.data 14 -edata {0 0 0 0 0 0 67 0 0 0 0 0 33 0} \
-rblk pc.data 14 -edata {0 0 0 0 0 0 67 0 31 0 0 0 0 0} \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 10 waddr 0 ainc 1]
#rlc log " A4: test clear -------------------------------------"
@@ -106,5 +109,5 @@ $cpu cp \
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "CLR"] \
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 3 ainc 1] \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 3 ainc 1] \
-rblk pc.data 14 -edata {0 0 0 0 0 0 0 0 0 0 0 0 0 0} \
-rblk pc.data 14 -edata {0 0 0 0 0 0 0 0 0 0 0 0 0 0} \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 10 waddr 0 ainc 1]

359
tools/tbench/w11a_pcnt/test_pcnt_codes.tcl Normal file
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@@ -0,0 +1,359 @@
# $Id: test_pcnt_codes.tcl 1053 2018-10-06 20:34:52Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2018-10-06 1053 1.0 Initial version
#
# Test perf counter functionality with test codes
# ----------------------------------------------------------------------------
rlc log "test_pcnt_codes: test counters --------------------------------------"
if {[$cpu get haspcnt] == 0} {
rlc log " test_pcnt_regs-W: no pcnt unit found, test aborted"
return
}
# define tmpproc for execute test
proc tmpproc_dotest {cpu code args} {
# compile and load code
$cpu cp -creset
$cpu ldasm -lst lst -sym sym $code
# clear and start dmpcnt
$cpu cp \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "CLR"}] \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STA"}]
# run code
rw11::asmrun $cpu sym
rw11::asmwait $cpu sym
# determine pcnt index range to read
set imin 31
set imax 0
foreach {nam val} $args {
if {! [info exists rw11::pcnt_cindex($nam)]} {
rlc log "FAIL: invalid counter name '$nam'"
rlc errcnt -inc
return
}
set i $rw11::pcnt_cindex($nam)
set imin [expr {min($imin,$i)}]
set imax [expr {max($imax,$i)}]
}
set nwrd [expr {2*($imax-$imin+1)}]
if {$nwrd <= 0} {
rlc log "FAIL: no counters to inspect"
rlc errcnt -inc
return
}
# stop dmpcnt and read counters
$cpu cp \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}] \
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr $imin ainc 1] \
-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr $imin waddr 0 ainc 1] \
-rblk pc.data $nwrd pcnt
## puts [rw11::pc_printraw]
# inspect counters
foreach {nam exp} $args {
set i0 [expr {2*($rw11::pcnt_cindex($nam)-$imin)}]
set i1 [expr {$i0+1}]
set v [expr {[lindex $pcnt $i0] + 65536.*[lindex $pcnt $i1]}]
if {$exp >= 0} {
if {$v != $exp} {
rlc log -bare \
[format "FAIL: $nam expect == $exp, found %1.0f" $v]
rlc errcnt -inc
}
} else {
if {$v <= -$exp} {
rlc log -bare \
[format "FAIL: $nam expect >= %d, found %1.0f" [expr {-$exp}] $v]
rlc errcnt -inc
}
}
}
}
# -- Section A ---------------------------------------------------------------
rlc log " A: plain kernel mode codes---------------------------------"
rlc log " A1: plain sob loop ---------------------------------"
set code {
. = 1000
stack:
start: mov #32.,r0
1$: sob r0,1$
halt
stop:
}
# cpu_idec: 34 = 32(sob) + 2(mov+halt)
# ca_rd: 35 = 2(mov) + 32(sob) + 1(halt)
tmpproc_dotest $cpu $code \
cpu_km_prix 0 \
cpu_km_pri0 -1 \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 34 \
cpu_vfetch 0 \
cpu_irupt 0 \
cpu_pcload 31 \
ca_rd 35 \
ca_wr 0 \
ca_rdhit 35 \
ca_wrhit 0 \
ca_rdmem 0 \
ca_wrmem 0
rlc log " A2: sob + inc R loop -------------------------------"
set code {
. = 1000
stack:
start: mov #32.,r0
clr r1
1$: inc r1
sob r0,1$
halt
stop:
}
# cpu_idec: 67 = 64(inc+sob) + 2(mov+clr+halt)
# ca_rd: 68 = 3(mov+clr) + 64(inc+sob) + 1(halt)
tmpproc_dotest $cpu $code \
cpu_km_prix 0 \
cpu_km_pri0 -1 \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 67 \
cpu_pcload 31 \
cpu_vfetch 0 \
cpu_irupt 0 \
ca_rd 68 \
ca_wr 0 \
ca_rdhit 68 \
ca_wrhit 0 \
ca_rdmem 0 \
ca_wrmem 0
rlc log " A3: sob + inc mem loop -----------------------------"
set code {
. = 1000
stack:
start: mov #32.,r0
clr cnt
1$: inc cnt
sob r0,1$
halt
stop:
cnt: .word 0
}
# cpu_idec: 67 = 64(inc+sob) + 2(mov+clr+halt)
# ca_rd: 133 = 4(mov+clr) + 128(inc+sob) + 1(halt)
tmpproc_dotest $cpu $code \
cpu_km_prix 0 \
cpu_km_pri0 -1 \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 67 \
cpu_pcload 31 \
cpu_vfetch 0 \
cpu_irupt 0 \
ca_rd 133 \
ca_wr 33 \
ca_rdhit 133 \
ca_wrhit 33 \
ca_rdmem 0 \
ca_wrmem 33
rlc log " A4: dec+bne+inc @#ibus loop (test ibus access) -----"
# use usr d page addr register (16 bit read/write) as easy ibus target
set code {
.include |lib/defs_mmu.mac|
. = 1000
stack:
start: mov #32.,r0
clr @#udpar
1$: inc @#udpar
dec r0
bne 1$
halt
stop:
cnt: .word 0
}
# cpu_idec: 99 = 96(inc+dec+bne) + 3(mov+clr+halt)
# ca_rd: 101 = 4(mov+clr) + 128(inc+dec+bne) + 1(halt)
tmpproc_dotest $cpu $code \
cpu_km_prix 0 \
cpu_km_pri0 -1 \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 99 \
cpu_pcload 31 \
cpu_vfetch 0 \
cpu_irupt 0 \
ca_rd 133 \
ca_wr 0 \
ca_rdhit 133 \
ca_wrhit 0 \
ca_rdmem 0 \
ca_wrmem 0 \
ib_rd 32 \
ib_wr 33
# -- Section B ---------------------------------------------------------------
rlc log " B: test kern pri>0, super and user mode -------------------"
rlc log " B1: kernel pri > 0 ---------------------------------"
set code {
.include |lib/defs_cpu.mac|
. = 1000
stack:
start: mov #cp.pr7,@#cp.psw
nop
nop
nop
nop
mov #cp.pr0,@#cp.psw
halt
stop:
}
tmpproc_dotest $cpu $code \
cpu_km_prix -1 \
cpu_km_pri0 -4 \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 7 \
cpu_vfetch 0 \
cpu_irupt 0 \
cpu_pcload 0 \
ca_rd 11 \
ca_wr 0 \
ca_rdhit 11 \
ca_wrhit 0 \
ca_rdmem 0 \
ca_wrmem 0
rlc log " B2: supervisor mode --------------------------------"
set code {
.include |lib/defs_cpu.mac|
. = 1000
stack:
start: mov #cp.cms,@#cp.psw
nop
nop
nop
nop
mov #cp.pr0,@#cp.psw
halt
stop:
}
tmpproc_dotest $cpu $code \
cpu_km_prix 0 \
cpu_km_pri0 -1 \
cpu_km_wait 0 \
cpu_sm -4 \
cpu_um 0 \
cpu_idec 7 \
cpu_vfetch 0 \
cpu_irupt 0 \
cpu_pcload 0 \
ca_rd 11 \
ca_wr 0 \
ca_rdhit 11 \
ca_wrhit 0 \
ca_rdmem 0 \
ca_wrmem 0
rlc log " B3: user mode --------------------------------------"
set code {
.include |lib/defs_cpu.mac|
. = 1000
stack:
start: mov #cp.cmu,@#cp.psw
nop
nop
nop
nop
mov #cp.pr0,@#cp.psw
halt
stop:
}
tmpproc_dotest $cpu $code \
cpu_km_prix 0 \
cpu_km_pri0 -1 \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um -4 \
cpu_idec 7 \
cpu_vfetch 0 \
cpu_irupt 0 \
cpu_pcload 0 \
ca_rd 11 \
ca_wr 0 \
ca_rdhit 11 \
ca_wrhit 0 \
ca_rdmem 0 \
ca_wrmem 0
# -- Section C ---------------------------------------------------------------
rlc log " C: test vector fetch --------------------------------------"
rlc log " C1: vector via trap instruction --------------------"
set code {
.include |lib/vec_cpucatch.mac|
. = 1000
stack:
start: mov #vh.trp,@#v..trp
mov #vh.emt,@#v..emt
clr r0
trap 1
emt 1
trap 2
emt 2
halt
stop:
vh.trp: rti
vh.emt: inc r0
rti
}
# cpu_idec: 14 = 8(main) +2*1(trap) + 2*2(emt)
# ca_rd: 34 = 14+4(code) + 4*2(trap+emt) + 4*2(rti)
# ca_wr: 34 = 2(code) + 4*2(trap+emt)
# ca_pcload: 8 = 4(trap+emt) + 4(rti)
tmpproc_dotest $cpu $code \
cpu_km_prix 0 \
cpu_km_pri0 -1 \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 14 \
cpu_vfetch 4 \
cpu_irupt 0 \
cpu_pcload 8 \
ca_rd 34 \
ca_wr 10 \
ca_rdhit 34 \
ca_wrhit 10 \
ca_rdmem 0 \
ca_wrmem 10

10
tools/tbench/w11a_pcnt/test_pcnt_regs.tcl
View File

@@ -1,11 +1,12 @@
# $Id: test_pcnt_regs.tcl 1050 2018-09-23 15:46:42Z mueller $
# $Id: test_pcnt_regs.tcl 1053 2018-10-06 20:34:52Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2018-09-23 1450 1.0 Initial version
# 2018-10-06 1053 1.0 Initial version
# 2018-09-23 1050 0.1 First draft
#
# Test register response
@@ -21,14 +22,15 @@ if {[$cpu get haspcnt] == 0} {
rlc log " A basic register access tests -----------------------------"
rlc log " A1: write cntl, read stat --------------------------"
# test start,stop works and run flag follows
# test start,stop works and run flag follows; test cntl readable (no check)
$cpu cp \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "CLR"}] \
-rreg pc.stat -edata [regbld rw11::PC_STAT] \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STA"}] \
-rreg pc.stat -edata [regbld rw11::PC_STAT run] \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}] \
-rreg pc.stat -edata [regbld rw11::PC_STAT]
-rreg pc.stat -edata [regbld rw11::PC_STAT] \
-rreg pc.cntl
# test that load works, caddr and ainc follow in status, and that clr clears
$cpu cp \
-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 0x07 ainc 0] \

3
tools/tbench/w11a_pcnt/w11a_pcnt_all.dat
View File

@@ -1,7 +1,8 @@
# $Id: w11a_pcnt_all.dat 1050 2018-09-23 15:46:42Z mueller $
# $Id: w11a_pcnt_all.dat 1053 2018-10-06 20:34:52Z mueller $
#
## steering file for all w11a_pcnt tests
#
test_pcnt_regs.tcl
test_pcnt_basics.tcl
test_pcnt_codes.tcl
#

28
tools/tcl/rw11/dmpcnt.tcl
View File

@@ -1,4 +1,4 @@
# $Id: dmpcnt.tcl 1051 2018-09-29 15:29:11Z mueller $
# $Id: dmpcnt.tcl 1053 2018-10-06 20:34:52Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,7 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2018-09-29 1051 1.0 Initial version
# 2018-10-06 1053 1.0 Initial version
# 2018-09-23 1050 0.1 First draft
#
@@ -31,14 +31,22 @@ namespace eval rw11 {
regdsc PC_STAT {ainc 15} {caddr 13 5} {waddr 8} {run 0}
# preliminary handling of counter names, hack in first version
variable pcnt_cnames {cpu_cpbusy cpu_km_prix cpu_km_pri0 cpu_km_wait \
cpu_sm cpu_um cpu_idec cpu_vfetch \
cpu_irupt cpu_pcload ca_rd ca_wr \
ca_rdhit -ca_wrhit -ca_rdmem -ca_wrmem \
-ca_rdwait -ca_wrwait ib_rd ib_wr \
ib_busy rb_rd rb_wr rb_busy \
-ext_rdrhit -ext_wrrhit -ext_wrflush -ext_rlrdbusy \
-ext_rlrdback -ext_rlwrbusy -ext_rlwrback clock}
variable pcnt_cnames [list cpu_cpbusy cpu_km_prix cpu_km_pri0 cpu_km_wait \
cpu_sm cpu_um cpu_idec cpu_pcload \
cpu_vfetch cpu_irupt ca_rd ca_wr \
ca_rdhit ca_wrhit ca_rdmem ca_wrmem \
ca_rdwait ca_wrwait ib_rd ib_wr \
ib_busy rb_rd rb_wr rb_busy \
ext_rdrhit ext_wrrhit ext_wrflush ext_rlrdbusy \
ext_rlrdback ext_rlwrbusy ext_rlwrback clock]
variable pcnt_cindex
set tmp_ind 0
foreach {nam} $pcnt_cnames {
set pcnt_cindex($nam) $tmp_ind
incr tmp_ind
}
unset tmp_ind
#
# pc_setup: rmap definitions for dmpcnt
#