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pdp11_sequencer: BUGFIX: correct mmu trap vs interrupt priority
- rtl/w11a/pdp11_sequencer: BUGFIX: correct mmu trap vs interrupt priority - tools/asm-11/lib/halt_checks.mac: add htstge - tools/tcode - cpu_details.mac: add test A1.2 - cpu_mmu.mac: add test E2.1
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wfjm
@@ -1,4 +1,4 @@
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; $Id: cpu_details.mac 1320 2022-11-22 18:52:59Z mueller $
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; $Id: cpu_details.mac 1322 2022-11-28 19:31:57Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -143,6 +143,25 @@ ta0101: mov #1000$,v..pir ; set up handler
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;
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9999$: iot ; end of test A1.1
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;
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; Test A1.2 -- PIRQ and immediate interrupt ++++++++++++++++++++++++++
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; This test verifies that an interrupt is taken immediately after the
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; write of the PIRQ register
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;
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ta0102: spl 0 ; ensure execution at PR0
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mov #1000$,v..pir ; set up handler
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mov #cp.pr7,v..pir+2 ; which runs at pr7
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mov #pi.r03,cp.pir ; request PIRQ 3
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halt ; halt if not taken immediatly
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;
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1000$: clr cp.pir ; cancel all PIRQ levels
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mov #1100$,(sp) ; continue
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rti
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;
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1100$: mov #v..pir+2,v..pir; restore pirq vector catcher
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clr v..pir+2
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;
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9999$: iot ; end of test A1.2
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;
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; Test A2: CPUERR +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies operation of CPUERR register
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;
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@@ -947,7 +966,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#23. ; all tests done ?
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hcmpeq tstno,#24. ; all tests done ?
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;
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jmp loop
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;
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@@ -1,4 +1,4 @@
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; $Id: cpu_mmu.mac 1321 2022-11-24 15:06:47Z mueller $
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; $Id: cpu_mmu.mac 1322 2022-11-28 19:31:57Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -1408,6 +1408,7 @@ td0101:
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; Section E: traps and pdr aia and aiw bits ==================================
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;
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; Test E1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Check basic MMU trap and PDR aia/aiw logic
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;
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; Test E1.1 -- test m0.trp, pdr aia/aiw transitions ++++++++++++++++++
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; Summary
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@@ -1757,7 +1758,7 @@ te0104: mov #<127.*md.plf>!md.att,kipdr5 ; enable traps (afc=4)
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mov #1000$,r3 ; ptr to failed landing
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mov #vhmmut,v..mmu ; setup MMU trap handler
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mov #1100$,vhvmmu
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jmp @#p5base-6 ; start test code
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jmp @#p5ce14 ; start test code
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;
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1000$: nop ; lands here if no trap
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halt
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@@ -1767,6 +1768,54 @@ te0104: mov #<127.*md.plf>!md.att,kipdr5 ; enable traps (afc=4)
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mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5
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mov #v..mmu+2,v..mmu
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;
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9999$: iot ; end of test E1.4
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;
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; Test E2: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Check MMU trap priority behavior
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;
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; common handler setup for trap and interrupt priority tests
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;
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mov #vhtmmu,v..mmu ; mmu trap handler
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mov #cp.pr7,v..mmu+2 ; run at PR7 (lockout PIRQ)
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mov #vhtpir,v..pir ; PIRQ handler
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mov #cp.pr7,v..pir+2 ; run at PR7 (prevent retrigger)
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mov #<127.*md.plf>!md.att,kipdr5 ; enable traps in page 5 (afc=4)
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;
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; Test E2.1 -- mmu trap + interrupt priority +++++++++++++++++++++++++
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;
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te0201: mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18
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mov #1500$,r5 ; set up data pointer
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;
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spl 0 ; ensure PR0
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call p5ce21 ; start probe code in page 5
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1000$: br 2000$ ; rts will land here
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;
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1500$: .word 0,0 ; 1st marker (MMU for movb)
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.word 0,0 ; 2nd marker (PIRQ)
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.word 0,0 ; 3rd marker (MMU for rts)
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.word -1,-1 ; fence
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;
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2000$: hcmpeq #1500$+12.,r5 ; check 3 markers expected
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mov #1500$,r5
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hcmpeq #250,(r5)+ ; 1st: MMU for movb
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hcmpeq #p5ce21+6,(r5)+ ; PC after movb
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hcmpeq #240,(r5)+ ; 2nd: PIRQ
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hcmpeq #p5ce21+6,(r5)+ ; PC after movb
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hcmpeq #250,(r5)+ ; 3rd: MMU for rts
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hcmpeq #1000$,(r5)+ ; PC after rts (the return address)
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;
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reset ; mmu off ;! MMU off
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;
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9999$: iot ; end of test E2.1
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;
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; common restore for section E2 --------------------------------------
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;
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mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5
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mov #v..mmu+2,v..mmu ; restore v..mmu to catcher
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clr v..mmu+2
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mov #v..pir+2,v..pir ; restore v..pir to catcher
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clr v..pir+2
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;
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; Section F: miscellaneous ===================================================
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;
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; Test F1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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@@ -1880,11 +1929,11 @@ tf0102: mov #154345,@#p6base ; inititialize target
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;; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#20. ; all tests done ?
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hcmpeq tstno,#22. ; all tests done ?
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;
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jmp loop
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;
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; kernel handlers ============================================================
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; kernel handlers and helpers ================================================
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;
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; vhmmua - expected mmu abort handler ++++++++++++++++++++++++++++++++++++++++
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; used to catch expected MMU aborts
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@@ -1939,6 +1988,28 @@ vhuemt: tst (sp)+ ; discard one word of vector push
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vhustp: .word vhuhlt
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vhuhlt: halt
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;
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; vhtmmu - handler for MMU trap tracing ++++++++++++++++++++++++++++++++++++++
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; Writes signature to data area (ptr in r5).
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; Signature is vector address + return PC (PC to test proper context).
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; Clears MMR0(trp) bit to allow further MMU traps
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;
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vhtmmu: htstge (r5) ; r5 at fence ?
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bic #m0.trp,mmr0 ; allow further MMU traps
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mov #250,(r5)+ ; track MMU vector
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mov (sp),(r5)+ ; track PC
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rti
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;
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; vhtpir - handler for PIRQ interrupt tracing ++++++++++++++++++++++++++++++++
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; Writes signature to data area (ptr in r5).
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; Signature is vector address + return PC (PC to test proper context).
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; Clears all PIRQ requests to prevent interrupt loop.
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;
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vhtpir: htstge (r5) ; r5 at fence ?
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clr cp.pir ; clear all PIRQ interrupts
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mov #240,(r5)+ ; track PIRQ vector
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mov (sp),(r5)+ ; track PC
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rti
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;
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; Test codes that will be mapped in user or supervisor mode ==================
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; They are located in page 4 at 100000 and above and are position-independent
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; code. That allows to assemble and load them together with the main code.
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@@ -2009,12 +2080,11 @@ vc2dat: .word 010111
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.word 010333
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.word 010444
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;
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; Test E1.4 test code
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; p5ce14 Test E1.4 test code +++++++++++++++++++++++++++++++++++++++++
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; located at border of page 4 and page 5 (touching both)
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; started via @#p5base-6, therefore no explicit label
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;
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. = p5base-6
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inc r2 ; @117772; r2=1
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p5ce14: inc r2 ; @117772; r2=1
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inc r2 ; @117774; r2=2
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inc r2 ; @117776; r2=3
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inc r2 ; @120000; r2=4 <-- should trap here
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@@ -2022,5 +2092,10 @@ vc2dat: .word 010111
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inc r2 ; @120004; r2=6
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inc r2 ; @120006; r2=7
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jmp (r3) ; return to main code
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;
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; p5ce21 Test E2.1 test code +++++++++++++++++++++++++++++++++++++++++
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;
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p5ce21: movb #bit01,cp.pir+1 ; request PIRQ 1
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return ; and return to main flow
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;
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.end start
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