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Code Issues Releases Wiki Activity

minor updates

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- tb_pdp11core.vhd: print header
- vec_devcatch_reset.mac: finish half-done change start in commit a365317
This commit is contained in:
wfjm
2019-03-31 09:02:50 +02:00
parent 9411fe764d
commit f82736e5da
10 changed files with 107 additions and 43 deletions
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48
doc/README_known_issues.md
View File

@@ -7,6 +7,54 @@ This file descibes general issues.
The case id indicates the release when the issue was first recognized.
### V0.50-5 {[issue #25](https://github.com/wfjm/w11/issues/25)} -- CPU: The AIB bit in MMU SDR register set independant of ACF field
The MMU should set the AIB A bit in the the SDR only when _"trap condition is
met by the Access Control Field (ACF)"_. Thus for
```
ACF=001 read-only trap on read
ACF=100 read/write trap on read or write
ACF=101 read/write trap on write
```
The current pdp11_mmu implementation always sets the bit, the logic is simply
```
if doabort = '0' then
AIB_SETA <= '1';
AIB_SETW <= CNTL.wacc or CNTL.macc;
end if;
```
Since the MMU trap mechanism is is only available on 11/45 and 11/70, but not
in the J11, it is not used by common operating systems.
Therefore this is considered a to be a minor deficit. Will be fixed in an
upcoming release.
### V0.50-4 {[issue #24](https://github.com/wfjm/w11/issues/24)} -- CPU: src+dst deltas summed in ssr1 if register identical
Test 12 of maindec `ekbee1` fails because it expects after a
```
mov #100000,@#ssr0
```
which sets an error bit in `ssr0` and thus freezes `ssr0`, that `ssr1` contains
```
013427 (00010 111 00010 111) (+2,r7;+2,r7)
```
while w11a gives
```
000047 (00000 000 00100 111) (--,--;+4,r7)
```
The `ssr1` content is _different_ compared to the original 11/70 behavior,
but is _logically correct_, fault recovery in OS (like in 211bsd) will work
correctly. Therefore this is considered a to be a _minor deficit_.
The 11/70 documentation clearly states that there is an additional state bit
that counts the write accesses to `ssr1`. This ensures that each of the two
logged accesses end in separate bytes (byte 0 filled first).
The w11a only uses byte 1 when the register number differs.
### V0.50-1 {[issue #23](https://github.com/wfjm/w11/issues/23)} -- CPU: several deficits in trap logic
The current w11a implementation has several deficits in the handling of

20
doc/w11a_known_issues.md
View File

@@ -71,17 +71,6 @@ basic hardware tests are sensitive to this.
- **TCK-030 pri=L: CPU: `SSR0` trap bit set when access aborted**
The 'trap bit' (bit 12: 10000) is set even when the access is aborted.
- **TCK-029 pri=L: CPU: `AIB` `A` bit set for all accesses**
The MMU trap condition isn't properly decoded
- **TCK-028 pri=H: CPU: interrupt and trap precedence**
In case of multiple trap, fault, or interrupt conditions the precedence
isn't implemented correctly.
- **TCK-026 pri=L: CPU: src+dst delta added in `SSR1` when same register**
The `SSR1` content after a fault is logically correct in w11a, but
different from 11/70.
- **TCK-025 pri=L: CPU: no mmu trap when bit9 clearing instruction traps**
In the 11/70 the instruction which affects mmu trap can cause a trap
already, in w11a only the next instruction will trap.
@@ -89,12 +78,3 @@ already, in w11a only the next instruction will trap.
- **TCK-014 pri=M: RK11: write protect action too slow**
Some simple RK11 drivers, especially in tests, don't poll for completion
of a write protect command. Due to the emulated I/O this can cause errors.
- The last four issues are caused by an incorrect implementation of the trap
logic, which leads to a different precendence when multiple trap, fault,
or interrupt occur
- **TCK-007 pri=H: CPU: no trap-4 after emt on odd stack**
- **TCK-006 pri=H: CPU: no yel-stack trap after `jsr pc,nnn(pc)`**
- **TCK-004 pri=H: CPU: yel-stack by interrupt causes loop-up**
- **TCK-003 pri=H: CPU: yel-stack by `IOT` pushes two stack frames**

48
rtl/w11a/tb/tb_pdp11core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_pdp11core.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: tb_pdp11core.vhd 1124 2019-03-24 21:20:33Z mueller $
--
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -47,6 +47,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-17 1123 1.5.1 print header
-- 2015-05-08 675 1.5 start/stop/suspend overhaul
-- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
@@ -228,7 +229,48 @@ begin
RESET <= '0';
wait for 9*clock_period;
-- write header
write(oline, string'(" # cycles"));
writeline(output, oline);
write(oline, string'(" | function"));
writeline(output, oline);
write(oline, string'(" | | register"));
writeline(output, oline);
write(oline, string'(" | | | input data"));
writeline(output, oline);
write(oline, string'(" | | | | cmdbusy"));
writeline(output, oline);
write(oline, string'(" | | | | | cmdack"));
writeline(output, oline);
write(oline, string'(" | | | | | | cmderr"));
writeline(output, oline);
write(oline, string'(" | | | | | | | cmdmerr"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | output data"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | cpugo"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |cpustep"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | ||cpuwait"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |||cpususp"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | ||||suspint"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |||||suspext"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| cpurust"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| | Check result"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| | |"));
writeline(output, oline);
file_loop: while not endfile(ifile) loop
-- this logic is a quick hack to implement the 'stapc' command

6
tools/asm-11/lib/vec_devcatch_reset.mac
View File

@@ -1,5 +1,5 @@
; $Id: vec_devcatch_reset.mac 1122 2019-03-17 08:15:42Z mueller $
; Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
; $Id: vec_devcatch_reset.mac 1124 2019-03-24 21:20:33Z mueller $
; Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
; License disclaimer see License.txt in $RETROBASE directory
;
; re-write vector catcher for device interrupts (subset used by w11)
@@ -20,7 +20,7 @@
clr v..kwp+2
;
mov #v..xu+2,v..xu ; vec 120 (DEUNA)
clr v..deu+2
clr v..xu+2
;
mov #v..rl+2,v..rl ; vec 160 (RL11)
clr v..rl+2

7
tools/src/librtools/ReventFd.cpp
View File

@@ -1,6 +1,6 @@
// $Id: ReventFd.cpp 1089 2018-12-19 10:45:41Z mueller $
// $Id: ReventFd.cpp 1125 2019-03-30 07:34:54Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
@@ -19,7 +19,6 @@
// ---------------------------------------------------------------------------
/*!
\file
\brief Implemenation of class ReventFd.
*/
@@ -29,7 +28,7 @@
#include "ReventFd.hpp"
#include "librtools/Rexception.hpp"
#include "Rexception.hpp"
using namespace std;

3
tools/src/librtools/ReventFd.hpp
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@@ -1,4 +1,4 @@
// $Id: ReventFd.hpp 1084 2018-12-16 12:23:53Z mueller $
// $Id: ReventFd.hpp 1125 2019-03-30 07:34:54Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@@ -20,7 +20,6 @@
/*!
\file
\brief Declaration of class \c ReventFd.
*/

3
tools/src/librtools/ReventFd.ipp
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@@ -1,4 +1,4 @@
// $Id: ReventFd.ipp 983 2018-01-02 20:35:59Z mueller $
// $Id: ReventFd.ipp 1125 2019-03-30 07:34:54Z mueller $
//
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@@ -18,7 +18,6 @@
// ---------------------------------------------------------------------------
/*!
\file
\brief Implemenation (inline) of class ReventFd.
*/

7
tools/src/librtools/RtimerFd.cpp
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@@ -1,6 +1,6 @@
// $Id: RtimerFd.cpp 983 2018-01-02 20:35:59Z mueller $
// $Id: RtimerFd.cpp 1125 2019-03-30 07:34:54Z mueller $
//
// Copyright 2013-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,6 @@
// ---------------------------------------------------------------------------
/*!
\file
\brief Implemenation of class RtimerFd.
*/
@@ -28,7 +27,7 @@
#include "RtimerFd.hpp"
#include "librtools/Rexception.hpp"
#include "Rexception.hpp"
using namespace std;

5
tools/src/librtools/RtimerFd.hpp
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@@ -1,4 +1,4 @@
// $Id: RtimerFd.hpp 1084 2018-12-16 12:23:53Z mueller $
// $Id: RtimerFd.hpp 1125 2019-03-30 07:34:54Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@@ -20,7 +20,6 @@
/*!
\file
\brief Declaration of class \c RtimerFd.
*/
@@ -29,7 +28,7 @@
#include <time.h>
#include "librtools/Rtime.hpp"
#include "Rtime.hpp"
namespace Retro {

3
tools/src/librtools/RtimerFd.ipp
View File

@@ -1,4 +1,4 @@
// $Id: RtimerFd.ipp 983 2018-01-02 20:35:59Z mueller $
// $Id: RtimerFd.ipp 1125 2019-03-30 07:34:54Z mueller $
//
// Copyright 2013-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@@ -18,7 +18,6 @@
// ---------------------------------------------------------------------------
/*!
\file
\brief Implemenation (inline) of class RtimerFd.
*/