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*.mac: ssr->mmr rename

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wfjm
2022-08-09 10:13:07 +02:00
parent e8fc9fa366
commit fc10cc5321
4 changed files with 74 additions and 71 deletions
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11
tools/tbench/w11a/test_w11a_cpuerr.tcl
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@@ -1,9 +1,10 @@
# $Id: test_w11a_cpuerr.tcl 1254 2022-07-13 06:16:19Z mueller $
# $Id: test_w11a_cpuerr.tcl 1272 2022-08-07 17:37:51Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2016-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-06 1272 1.0.1 ssr->mmr rename
# 2016-12-27 831 1.0 Initial version
#
# Test cpuerr register
@@ -57,15 +58,15 @@ t.002:
;
jsr pc, mminki ; init MMU, kernel I space only
mov #177400,@#kipar+014 ; kipar(6): to page below I/O page
mov #m3.e22,@#ssr3 ; enable 22bit
mov #m0.ena,@#ssr0 ; enable MMU
mov #m3.e22,@#mmr3 ; enable 22bit
mov #m0.ena,@#mmr0 ; enable MMU
;
mov #t.004,r4 ; setup continuation address
mov #140000,r0 ; r0 points to non-existent memory
tst (r0) ; access
; !! will trap to 004 and set 000040 !!
halt ; blocker
t.004: clr @#ssr0 ; disable MMU
t.004: clr @#mmr0 ; disable MMU
;
; test 005: I/O bus timeout abort; will set bit cp.ito -----------------------
;

27
tools/tbench/w11a_cmon/test_cmon_logs.tcl
View File

@@ -1,9 +1,10 @@
# $Id: test_cmon_logs.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_cmon_logs.tcl 1272 2022-08-07 17:37:51Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-06 1272 2.0.1 ssr->mmr rename
# 2017-04-23 885 2.0 adopt to revised interface
# 2015-08-02 707 1.0 Initial version
#
@@ -578,19 +579,19 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
mov #<77400+md.arw>,@#<kipdr+16> ; s7: slf=127; ed=0; acf=rw
mov #177600,@#<kipar+16> ; to io page (22 bit)
mov #234,vtst
mov #m3.e22,@#ssr3 ; enable 22bit mode
mov #<m0.ent+m0.ena>,@#ssr0 ; enable mmu, enable traps
mov #m3.e22,@#mmr3 ; enable 22bit mode
mov #<m0.ent+m0.ena>,@#mmr0 ; enable mmu, enable traps
;
mov vtst,r0 ; no trap (is read)
inc r0
mov r0,vtst ; should trap (is write)
inc vtst ; should trap (is read-mod-write)
;
clr @#ssr0
clr @#mmr0
halt
stop:
;
vh.mmu: mov #<m0.ent+m0.ena>,@#ssr0 ; clear error flags, keep enables
vh.mmu: mov #<m0.ent+m0.ena>,@#mmr0 ; clear error flags, keep enables
rti
;
vh.xxx: halt
@@ -776,8 +777,8 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
mov #077400,@#<kipdr+02> ; s1: slf=127; ed=0; acf=abo
mov #<77400+md.arw>,@#<kipdr+16> ; s7: slf=127; ed=0; acf=rw
mov #177600,@#<kipar+16> ; to io page (22 bit)
mov #m3.e22,@#ssr3 ; enable 22bit mode
mov #m0.ena,@#ssr0 ; enable mmu
mov #m3.e22,@#mmr3 ; enable 22bit mode
mov #m0.ena,@#mmr0 ; enable mmu
;
mov #bad,r5 ; to blocker
mov vok,a ; should be ok
@@ -787,7 +788,7 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
ok: mov #bad,r5 ; to blocker
mov vok,a ; should be ok again
;
clr @#ssr0
clr @#mmr0
halt
stop:
bad: halt
@@ -795,10 +796,10 @@ bad: halt
a: .word 0
b: .word 0
;
vh.mmu: mov @#ssr0,r0 ; check ssr0
mov @#ssr1,r1 ; check ssr1
mov @#ssr2,r2 ; check ssr2
mov #m0.ena,@#ssr0 ; clear error flags, keep enable
vh.mmu: mov @#mmr0,r0 ; check mmr0
mov @#mmr1,r1 ; check mmr1
mov @#mmr2,r2 ; check mmr2
mov #m0.ena,@#mmr0 ; clear error flags, keep enable
mov r5,(sp) ; use recovery address
rti
;