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final round for initial tcode version
- tools/tcode - cpu_basics.mac: add A4.5 - cpu_details.mac: add B1.4, B2.3, B4.1-3 - cpu_mmu.mac: add B3.3 - cpu_selftest.mac: add B1
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@ -1,10 +1,10 @@
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; $Id: cpu_basics.mac 1344 2023-01-03 15:51:21Z mueller $
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; $Id: cpu_basics.mac 1345 2023-01-04 18:05:42Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2023-01-02 1342 1.0 Initial version
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; 2023-01-04 1345 1.0 Initial version
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; 2015-08-30 710 0.1 First draft
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;
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; Test CPU basics: most instructions except traps, EIS and FPP
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@ -31,6 +31,7 @@
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; A4.2 jsr + cc
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; A4.3 jsr r0-r5
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; A4.4 jsr sp and rts sp
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; A4.5 jsr r1,(r1)+
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; A5 mark
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;
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; Test A1: ccop + bxx +++++++++++++++++++++++++++++++++++++++++++++++++++++++
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@ -960,7 +961,7 @@ ta0403: clr 900$ ; reset call counter
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; Test A4.4 -- jsr sp and rts sp ++++++++++++++++++++++++++++++++++++++
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; In case of jsr sp and rts sp, the sp register is used both as linkage
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; register and implicitly as stack pointer. That interferes and gives
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; quite bizarre semantics, certainly never used, but should work
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; quite bizarre behavior, certainly never used, but should work
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; - jsr sp,<dst> will
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; - push current SP onto stack
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; - set SP to the location of following instruction
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@ -1000,6 +1001,24 @@ ta0404: hcmpeq sp,#stack ; check stack is default
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;
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9999$: iot ; end of test A4.4
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;
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; Test A4.5 -- jsr r1,(r1)+ ++++++++++++++++++++++++++++++++++++++++++
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; Using the same register in the destination specifier and as linkage
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; register is possible and works as usual.
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;
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ta0405: mov #200$,r1
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jsr r1,(r1)+ ; calls 200$
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100$: .word 000301 ; 1st arg
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.word 000302 ; 2nd arg
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hcmpeq #200$+2,r1 ; check that incremented r1 restored
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br 9999$
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;
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200$: hcmpeq #100$,r1 ; check r1 holds address after jsr
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hcmpeq #301,(r1)+ ; process 1st arg
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hcmpeq #302,(r1)+ ; process 1st arg
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rts r1
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;
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9999$: iot ; end of test A4.5
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;
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; Test A5 -- mark ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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@ -3575,7 +3594,7 @@ tf0406: mov #100$,r1 ; dst for (r1)
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#60. ; all tests done ?
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hcmpeq tstno,#61. ; all tests done ?
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;
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jmp loop
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;
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@ -1,10 +1,10 @@
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; $Id: cpu_details.mac 1343 2023-01-02 18:03:39Z mueller $
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; $Id: cpu_details.mac 1345 2023-01-04 18:05:42Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2023-01-02 1343 1.0 Initial version
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; 2023-01-04 1345 1.0 Initial version
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; 2022-07-18 1259 0.1 First draft
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;
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; Test CPU details
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@ -545,8 +545,8 @@ ta0302:
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hcmpeq #15.,342(r5) ; check 15th push (was done)
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hcmpeq #cp.pr6,340(r5) ; saved PS of attempted yellow trap
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htsteq 336(r5) ; red zone border clean ?
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;; hcmpeq #cp.pr6,@#2 ; saved PS of red abort (w11 not yet!)
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;; hcmpeq #200$,@#0 ; saved PC of red abort (e11 not yet!)
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hcmpeq #cp.pr6,@#2 ; saved PS of red abort
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hcmpeq #200$,@#0 ; saved PC of red abort
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dec r1 ; too far for sob
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beq 1020$
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jmp 100$ ; go for next STKLIM value
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@ -1534,14 +1534,16 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler
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;
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9999$: iot ; end of test A4.4
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;
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; Section B: Stress and fllow tests ==========================================
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; Section B: Stress and flow tests ===========================================
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; B1 address mode torture tests
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; B1.1 src-dst update hazards with (r0)+,(r0)
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; B1.2 (pc)+ as destination
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; B1.3 pc as destination in clr, mov, and add
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; B1.4 (pc)+ as destination case 2
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; B2 pipeline torture tests
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; B2.1 self-modifying code, use (pc), -(pc)
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; B2.2 self-modifying code, use (pc) case 2
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; B2.3 self-modifying code, use (pc) case 3
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; B3 specifier flow and abort tests
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; B3.1 dstw flow and cc
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; part 1: check cc for MOV for all modes
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@ -1553,6 +1555,10 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler
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; B3.4 dstr flow and cc
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; part 1: check cc for INC for all modes
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; part 2: check cc for INC after abort for all modes
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; B4 byte mode flow tests
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; B4.1 srcr and byte access
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; B4.2 dstr and byte access
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; B4.3 dstw and byte access
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;
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; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
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; This sub-section tests peculiar address node usage
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@ -1646,6 +1652,24 @@ tb0103: mov #000137,@#0 ; setup jmp 1000$ at mem(0)
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;
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9999$: iot ; end of test B1.3
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;
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; Test B1.4 -- (pc)+ as destination case 2 +++++++++++++++++++++++++++
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; 'inc #177777' seen as 're-entry protection' in several xxdp test codes
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;
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tb0104: mov #3,r0 ; try counter
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clr r1 ; 1st entry counter
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clr r2 ; other entry counter
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100$: inc #177777 ; value will be modified
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bne 200$ ; ne if not 1st entry
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inc r1 ; 1st entry
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br 300$
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200$: inc r2 ; other entries
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300$: sob r0,100$
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hcmpeq #1,r1 ; check 1st entry count
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hcmpeq #2,r2 ; check other entry count
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mov #177777,100$+2 ; restore
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;
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9999$: iot ; end of test B1.4
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;
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; Test B2: pipeline torture tests +++++++++++++++++++++++++++++++++++++++++++
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; This sub-section tests self-modifying code
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;
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@ -1708,6 +1732,18 @@ tb0202: mov #2,r5
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;
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9999$: iot ; end of test B2.2
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;
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; Test B2.3 -- self-modifying code, use (pc) case 3 ++++++++++++++++++
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; The 'mtpi (pc)' usage was seen in maindec-11-dekbb-c
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;
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tb0203: push #scc ; scc instruction
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clr cp.psw
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mtpi (pc)
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100$: halt ; will be overwritten
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hcmpeq #cpnzvc,cp.psw ; check that scc was executed
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clr 100$ ; restore
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;
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9999$: iot ; end of test B2.3
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;
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; Test B3: specifier flow and abort tests +++++++++++++++++++++++++++++++++++
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; This sub-section tests flow and cc properties
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;
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@ -1951,6 +1987,94 @@ tb0304: clr r0 ; src for INC
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;
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9999$: iot ; end of test B3.4
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;
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; Test B4: byte mode flow tests +++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies correct byte mode increment/decrement behavior.
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; Done by flow for srcr, dstr and dstw. The dsta flow does not access bytes.
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; Only address changes are checked with representative instructions. The
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; correct byte data behavior was already tested in cpu_basics on a per
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; instruction basis.
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;
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; Test B4.1 -- srcr and byte access ++++++++++++++++++++++++++++++++++
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;
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tb0401: mov #100$,r1 ; src for (r1)+,-(r1)
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mov #200$,r2 ; src for @(r2)+,@-(r2)
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;
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bisb (r1)+,r5 ; mode 2 gpr -> inc 1
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hcmpeq #100$+1,r1
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bisb -(r1),r5 ; mode 4 gpr -> dec 1
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hcmpeq #100$,r1
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;
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bisb @(r2)+,r5 ; mode 3 gpr -> inc 2
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hcmpeq #200$+2,r2
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bisb @-(r2),r5 ; mode 5 gpr -> dec 2
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hcmpeq #200$,r2
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;
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bisb -(sp),r5 ; mode 4 sp -> dec 2 (stupid case)
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hcmpeq #stack-2,sp
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bisb (sp)+,r5 ; mode 2 sp -> inc 2
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hcmpeq #stack,sp
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;
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br 9999$
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;
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100$: .word 0 ; src target
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200$: .word 100$ ; ptr to src
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;
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9999$: iot ; end of test B4.1
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;
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; Test B4.2 -- dstr and byte access ++++++++++++++++++++++++++++++++++
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;
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tb0402: mov #100$,r1 ; dst for (r1)+,-(r1)
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mov #200$,r2 ; dst for @(r2)+,@-(r2)
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;
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bisb r5,(r1)+ ; mode 2 gpr -> inc 1
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hcmpeq #100$+1,r1
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bisb r5,-(r1) ; mode 4 gpr -> dec 1
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hcmpeq #100$,r1
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;
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bisb r5,@(r2)+ ; mode 3 gpr -> inc 2
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hcmpeq #200$+2,r2
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bisb r5,@-(r2) ; mode 5 gpr -> dec 2
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hcmpeq #200$,r2
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;
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bisb r5,-(sp) ; mode 4 sp -> dec 2 (stupid case)
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hcmpeq #stack-2,sp
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bisb r5,(sp)+ ; mode 2 sp -> inc 2
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hcmpeq #stack,sp
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;
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br 9999$
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;
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100$: .word 0 ; dst target
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200$: .word 100$ ; ptr to dst
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;
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9999$: iot ; end of test B4.2
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;
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; Test B4.3 -- dstw and byte access ++++++++++++++++++++++++++++++++++
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;
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tb0403: mov #100$,r1 ; dst for (r1)+,-(r1)
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mov #200$,r2 ; dst for @(r2)+,@-(r2)
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;
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movb r5,(r1)+ ; mode 2 gpr -> inc 1
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hcmpeq #100$+1,r1
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movb r5,-(r1) ; mode 4 gpr -> dec 1
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hcmpeq #100$,r1
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;
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movb r5,@(r2)+ ; mode 3 gpr -> inc 2
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hcmpeq #200$+2,r2
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movb r5,@-(r2) ; mode 5 gpr -> dec 2
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hcmpeq #200$,r2
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;
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clrb -(sp) ; mode 4 sp -> dec 2
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hcmpeq #stack-2,sp
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clrb (sp)+ ; mode 2 sp -> inc 2 (stupid case)
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hcmpeq #stack,sp
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;
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br 9999$
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;
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100$: .word 0 ; dst target
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200$: .word 100$ ; ptr to dst
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;
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9999$: iot ; end of test B4.3
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;
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; Section C: 11/70 specifics =================================================
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; C1 Implementation differences
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; C1.1 Register used as source and changed in dst flow
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@ -2009,7 +2133,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#33. ; all tests done ?
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hcmpeq tstno,#38. ; all tests done ?
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;
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jmp loop
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;
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@ -1,10 +1,10 @@
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; $Id: cpu_mmu.mac 1344 2023-01-03 15:51:21Z mueller $
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; $Id: cpu_mmu.mac 1345 2023-01-04 18:05:42Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-12-25 1337 1.0 Initial version
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; 2023-01-04 1345 1.0 Initial version
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; 2022-07-24 1262 0.1 First draft
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;
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; Test CPU MMU: all aspects of the MMU
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@ -239,6 +239,7 @@ ta0102:
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; part 5: test MTPI,MFPI with @(sp)+
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; part 6: test MFPD,MFPI and MTPD,MTPI for sp register access
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; part 7: test MFPD,MFPI and MTPD,MTPI for register r0-r5 access
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; B3.3 test MFPI,MTPI with cm=pm=user
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; B4 invalid cpu mode 10
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; B4.1 check that cmode=10 causes abort
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; B4.2 check MFPI/MTPI SP response for pmode=10
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@ -468,8 +469,7 @@ tb0301:
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9999$: iot ; end of test B3.1
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;
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; Test B3.2 -- run code in user mode with D space; mfp*, mtp* ++++++++
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; code vc1 is executed in user and in supervisor mode
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; the code runs in seg0 with D space enabled
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; Code vc1 is executed in user mode, runs in page 0 with D space enabled.
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;
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; This test verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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@ -503,6 +503,7 @@ tb0302:
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clr -(sp) ; will start at 0
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rti ; and launch it
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halt
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;
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1000$: ; continuation point
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; check psw
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ccc ; clear cc -> psw reflects pm setting
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@ -661,6 +662,51 @@ tb0302:
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;
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9999$: iot ; end of test B3.2
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;
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; Test B3.3 -- test MFPI,MTPI with cm=pm=user ++++++++++++++++++++++++
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; Verifies that MFPI acts like MFPD when cm=pm=user and that MTPI has no
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; such restriction and can modify I space when PDR ACF allows.
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; Runs code vc4 with D space enabled, code in page 0 and data in page 1.
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;
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tb0303:
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; set up emt handler
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mov #vhuemt,v..emt
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clr v..emt+2 ; pr0 kernel
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; enable mmu
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mov #m3.dum,mmr3 ; user d dspace, no 22bit
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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; set up data
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clr vc4l1
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; set user mode pdr/par, I page 0 and D page 1
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mov #<8.*md.plf>!md.arw,uipdr0 ; I space writable
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mov #<vc4/100>,uipar0
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mov #<8.*md.plf>!md.arw,udpdr1
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mov #<vc4dat/100>,udpar1
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; start code in user mode
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mov #1000$,vhustp ; set up continuation address
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mov #<cp.cmu!cp.pmu>,-(sp) ; next psw: user mode
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clr -(sp) ; will start at 0
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rti ; and launch it
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halt
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;
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1000$: ; continuation point
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hcmpeq #040111,r0 ; check direct D space access to vc4v1
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hcmpeq #040222,r1 ; check MFPI access to vc4v2 (D instead of I!)
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hcmpeq #040333,r2 ; check MFPD access to vc4v3
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hcmpeq #040444,vc4l1 ; check modified vc4l1
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;
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; reset user mode pdr/par
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clr uipdr0
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clr uipar0
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clr udpdr1
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clr udpar1
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;
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reset ; mmu off ;! MMU off
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clr cp.psw ; crop pm in psw
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mov #v..emt+2,v..emt ; restore emt catcher
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clr v..emt+2
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;
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9999$: iot ; end of test B3.3
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;
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; Test B4: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Test invalid cpu mode 10
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;
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@ -2065,13 +2111,14 @@ td0201: tstb systyp ; skip if not on w11
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; trp=0;pdr 0 0 0 - any par write clears aia,aiw
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;
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; acf=4 ent=1 tst (r3) 1 0 1 yes trap taken, trp set, aia set
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; clr (r3) 1 1 1 no no trap, aia set
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; clr (r3) 1 1 1 no no trap (trp=1!), aia set
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; trp=0;pdr 0 0 0 - any pdr write clears aia,aiw
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; clr (r3) 1 1 1 yes trap taken, trp,aia,aiw set
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; tst (r3) 1 1 1 no no trap, no additional bits
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; tst (r3) 1 1 1 no no trap (trp=1!), no bits
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; trp=0;pdr 0 0 0 - any par write clears aia,aiw
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;
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; Uses page 6 with plf=1 and varying acf
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; Uses page 6 with plf=1 and varying acf.
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; Checks that m0.trp must be cleared before a 2nd MMU trap is taken
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;
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te0101: mov #vhmmut,v..mmu ; setup MMU trap handler
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clr v..mmu+2 ; pr0 kernel
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@ -2149,7 +2196,7 @@ te0101: mov #vhmmut,v..mmu ; setup MMU trap handler
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1010$: hbitne mmr0,#m0.trp ; check trp=1
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hcmpeq (r4),#md.plf!md.aia!md.att ; check aia=1
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;
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; clr (r3) 1 1 1 no no trap, aia set
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; clr (r3) 1 1 1 no no trap (trp=1!), aia set
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clr (r3) ; probe write
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hbitne mmr0,#m0.trp ; check trp=1
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hcmpeq (r4),#md.plf!md.aia!md.aiw!md.att ; check aia=1,aiw=1
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@ -2166,7 +2213,7 @@ te0101: mov #vhmmut,v..mmu ; setup MMU trap handler
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1020$: hbitne mmr0,#m0.trp ; check trp=1
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hcmpeq (r4),#md.plf!md.aia!md.aiw!md.att ; check aia=1,aiw=1
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;
|
||||
; tst (r3) 1 1 1 no no trap, no additional bits
|
||||
; tst (r3) 1 1 1 no no trap (trp=1!), no additional bits
|
||||
tst (r3) ; probe read
|
||||
hbitne mmr0,#m0.trp ; check trp=1
|
||||
hcmpeq (r4),#md.plf!md.aia!md.aiw!md.att ; check aia=1,aiw=1
|
||||
@ -2581,7 +2628,7 @@ tf0102: mov #154345,@#p6base ; inititialize target
|
||||
; END OF ALL TESTS - loop closure ============================================
|
||||
;
|
||||
mov tstno,r0 ; hack, for easy monitoring ...
|
||||
hcmpeq tstno,#31. ; all tests done ?
|
||||
hcmpeq tstno,#32. ; all tests done ?
|
||||
call chkpdr ; kernel pdr/par OK ?
|
||||
;
|
||||
jmp loop
|
||||
@ -2775,6 +2822,32 @@ vc3: htstge (r5) ; r5 at fence ?
|
||||
vc3l1: emt 100 ; delegate RTI to system service
|
||||
vc3l2: halt ; label after emt
|
||||
;
|
||||
; vc4 - MFPI/MTPI user mode test code ++ used from B3.3 ++++++++++++++++++++++
|
||||
; Returns all values to be checked in registers
|
||||
; r0: D space access to vc4v1
|
||||
; r1: MFPI read of vc4v2; I space requested, but D space received
|
||||
; r2: MFPD read of vc4v3
|
||||
;
|
||||
. = 106000 ; I space ------------------------------------
|
||||
vc4: mov #<vc4stk-vc4dat+p1base>,sp ; initialize stack
|
||||
mov @#vc4v1-vc4dat+p1base,r0 ; simple D space access
|
||||
mfpi @#vc4v2-vc4dat+p1base ; reads D space! I would abort!
|
||||
pop r1 ; save value
|
||||
mfpd @#vc4v3-vc4dat+p1base ; read D space
|
||||
pop r2 ; save value
|
||||
push #040444
|
||||
mtpi vc4l1 ; write to I space allowed
|
||||
emt 100 ; will end code
|
||||
;
|
||||
vc4l1: .word 0
|
||||
;
|
||||
. = 107000 ; D space ------------------------------------
|
||||
vc4dat: .blkw 16. ; small stack space
|
||||
vc4stk:
|
||||
vc4v1: .word 040111
|
||||
vc4v2: .word 040222
|
||||
vc4v3: .word 040333
|
||||
;
|
||||
; p5ce14 Test E1.4 test code +++++++++++++++++++++++++++++++++++++++++
|
||||
; located at border of page 4 and page 5 (touching both)
|
||||
;
|
||||
|
||||
@ -1,17 +1,21 @@
|
||||
; $Id: cpu_selftest.mac 1329 2022-12-11 17:28:28Z mueller $
|
||||
; $Id: cpu_selftest.mac 1345 2023-01-04 18:05:42Z mueller $
|
||||
; SPDX-License-Identifier: GPL-3.0-or-later
|
||||
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
;
|
||||
; Revision History:
|
||||
; Date Rev Version Comment
|
||||
; 2022-07-18 1258 1.0 Initial version
|
||||
; 2023-01-04 1345 1.0 Initial version
|
||||
; 2022-07-13 1254 0.1 First draft
|
||||
;
|
||||
; Test CPU basics
|
||||
;
|
||||
.include |lib/tcode_std_base.mac|
|
||||
.include |lib/defs_mmu.mac|
|
||||
;
|
||||
; Section A: Self-Test codes
|
||||
; Section A: self test codes
|
||||
; Section B: CPU probe codes
|
||||
;
|
||||
; Section A: self test codes =================================================
|
||||
; A1 11/34 self test
|
||||
; A2 11/70 self test
|
||||
;
|
||||
@ -213,7 +217,41 @@ ta0201:
|
||||
;
|
||||
9999$: iot ; end of test A2
|
||||
;
|
||||
; Section B: CPU probe codes =================================================
|
||||
; B1 2.11BSD 11/70 cpuprobe
|
||||
;
|
||||
; Test B1 -- 2.11BSD cpuprobe ++++++++++++++++++++++++++++++++++++++++
|
||||
; The key decisions of the 2.11BSD cpu model detection. Only the sequence
|
||||
; leading to a 11/70 detection is done, all other branches end in a halt.
|
||||
; Full code is in /usr/src/sys/pdpstand/M.s starting as cpuprobe.
|
||||
;
|
||||
tb0101: mov #1000$,v..iit ; vector 4 handler
|
||||
mov #1000$,v..rit ; vector 10 handler
|
||||
;
|
||||
tst @#ubmap ; look for unibus map
|
||||
tst @#kdpar+14 ; look for split I/D (check kdpar6)
|
||||
mov #100$,1100$ ; setup catcher
|
||||
mfpt ; only 22,44 and J11 have MFPT
|
||||
halt
|
||||
100$: br 1200$ ; that's all, should be a 11/70
|
||||
;
|
||||
1000$: mov 1100$,(sp) ; set up return
|
||||
bne 1010$ ; catcher set ?
|
||||
halt ; halt of none set
|
||||
1010$: clr 1100$ ; reset catcher
|
||||
rti
|
||||
;
|
||||
1100$: .word 0 ; catcher address
|
||||
;
|
||||
1200$: mov #v..iit+2,v..iit ; restore
|
||||
mov #v..rit+2,v..rit ; restore
|
||||
;
|
||||
9999$: iot ; end of test B1
|
||||
;
|
||||
; END OF ALL TESTS - loop closure --------------------------------------------
|
||||
;
|
||||
mov tstno,r0 ; hack, for easy monitoring ...
|
||||
hcmpeq tstno,#3. ; all tests done ?
|
||||
;
|
||||
jmp loop
|
||||
;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user