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275 Commits 1 Branch 40 Tags
bc150d2f57b1906f5cbe4bc6c2a82bc99f77dfd0
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2 Commits

Author SHA1 Message Date
wfjm
0e87dd8670 add sramif2migui: w11a SRAM to MIG UI interface core 2019-01-02 10:06:25 +01:00
wfjm
14362b2a56 Add basic DDR memory support 
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
 2018-12-31 10:00:14 +01:00