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14 Commits 1 Branch 40 Tags
f2d0f3962188a1af58a748875bda94eacd8b2cdc
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4 Commits

Author SHA1 Message Date
Walter F.J. Mueller
3f455d5236 - interim release w11a_V0.532 (untagged) 
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
 2011-11-20 12:31:43 +00:00
Walter F.J. Mueller
e15295649e - interim release w11a_V0.531 (untagged) 
- many small changes to prepare upcoming support for Spartan-6 and
  usage of Cypress FX2 USB interface on nexys2/3 and atlys boards
 2011-09-12 20:52:31 +00:00
Walter F.J. Mueller
16ce5b2091 - interim release w11a_V0.51 (untagged) 
- migrate to ibus protocol verion 2
  - nexys2 systems now with DCM derived system clock supported
  - sys_w11a_n2 now runs with 58 MHz clksys
 2010-11-27 23:17:50 +00:00
Walter F.J. Mueller
3335c61549 initial source upload (no docs yet) 2010-07-09 18:14:38 +00:00