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Code Issues Releases Wiki Activity

- interim release w11a_V0.532 (untagged)

Browse Source 
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
This commit is contained in:
Walter F.J. Mueller
2011-11-20 12:31:43 +00:00
parent e15295649e
commit 3f455d5236
166 changed files with 2672 additions and 1029 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
doc/INSTALL.txt
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@@ -1,4 +1,4 @@
# $Id: INSTALL.txt 408 2011-09-12 19:48:36Z mueller $
# $Id: INSTALL.txt 409 2011-09-17 10:40:55Z mueller $
Guide to install and build w11a systems, test benches and support software

27
doc/README.txt
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@@ -1,4 +1,4 @@
# $Id: README.txt 408 2011-09-12 19:48:36Z mueller $
# $Id: README.txt 428 2011-11-20 12:19:31Z mueller $
Release notes for w11a
@@ -60,7 +60,30 @@ Release notes for w11a
3. Change Log ----------------------------------------------------------------
- trunk (2011-09-11: svn rev 12(oc) 408(wfjm); untagged w11a_V0.531) +++++++++
- trunk (2011-11-20: svn rev 13(oc) 428(wfjm); untagged w11a_V0.532) +++++++++
- Summary
- generalized the 'human I/O' interface for s3board,nexys2/3 and atlys
- added test design for the 'human I/O' interface
- no functional change of w11a CPU core or any existing test systems
- New features
- new modules
- rtl/sys_gen/tst_snhumanio
- sub-tree with test design for 'human I/O' interface modules
- atlys, nexys2, and s3board directories contain the systems
for the respectice Digilent boards
- Changes
- functional changes
- use now 'a6' polynomial of Koopman et al for crc8 in rlink
- with one exception all vhdl sources use now numeric_std
- module renames:
vlib/xlib/dcm_sp_sfs_gsim -> vlib/xlib/dcm_sfs_gsim
vlib/xlib/dcm_sp_sfs_unisim -> vlib/xlib/dcm_sfs_unisim_s3e
vlib/xlib/tb/tb_dcm_sp_sfs -> vlib/xlib/tb/tb_dcm_sfs
- trunk (2011-09-11: svn rev 12(oc) 409(wfjm); untagged w11a_V0.531) +++++++++
- Summary
- Many small changes to prepare upcoming support for

4
doc/w11a_os_guide.txt
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@@ -1,4 +1,4 @@
# $Id: w11a_os_guide.txt 317 2010-07-22 19:36:56Z mueller $
# $Id: w11a_os_guide.txt 428 2011-11-20 12:19:31Z mueller $
Guide to run operating system images on w11a systems
@@ -82,7 +82,7 @@ Guide to run operating system images on w11a systems
4. 2.11BSD system ---------------------------------------------------------
- A disk set is available from
http://www-linux.gsi.de/~mueller/retro/oc_w11/data/211bsd_rkset.tgz
http://www-linux.gsi.de/~mueller/retro/oc_w11/data/211bsd_rkset.tgz
Download, unpack and copy the disk images (*.dsk) to
$RETROBASE/rtl/sys_gen/w11a/tb

22
doc/w11a_tb_guide.txt
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@@ -1,4 +1,4 @@
# $Id: w11a_tb_guide.txt 376 2011-04-17 12:24:07Z mueller $
# $Id: w11a_tb_guide.txt 428 2011-11-20 12:19:31Z mueller $
Guide to running w11a test benches
@@ -66,7 +66,7 @@ Guide to running w11a test benches
time tbw tb_serport_uart_rx |\
tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
-> 1269955.0 ns 63488: DONE
-> real 0m1.178s user 0m1.172s sys 0m0.020s
-> real 0m01.178s user 0m01.172s sys 0m00.020s
- serport receiver/transmitter test
@@ -74,14 +74,14 @@ Guide to running w11a test benches
time tbw tb_serport_uart_rxtx |\
tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
-> 52335.0 ns 2607: DONE
-> real 0m0.094s user 0m0.092s sys 0m0.008s
-> real 0m00.094s user 0m00.092s sys 0m00.008s
- serport autobauder test
make tb_serport_autobaud
time tbw tb_serport_autobaud |\
tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)"
-> 367475.0 ns 18364: DONE
-> real 0m0.610s user 0m0.612s sys 0m0.004s
-> real 0m00.610s user 0m00.612s sys 0m00.004s
- rlink core test
@@ -90,7 +90,7 @@ Guide to running w11a test benches
time tbw tb_rlink_direct |\
tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
-> 142355.0 ns 7108: DONE
-> real 0m0.317s user 0m0.324s sys 0m0.028s
-> real 0m00.317s user 0m00.324s sys 0m00.028s
- rlink core test via serial port interface
@@ -98,12 +98,12 @@ Guide to running w11a test benches
time tbw tb_rlink_serport tb_rlink_serport_stim.dat |\
tee tb_rlink_serport_stim2_dsim.log | egrep "(FAIL|DONE)"
-> 72735.0 ns 3627: DONE
-> real 0m0.266s user 0m0.264s sys 0m0.008s
-> real 0m00.266s user 0m00.264s sys 0m00.008s
time tbw tb_rlink_serport tb_rlink_stim.dat |\
tee tb_rlink_serport_dsim.log | egrep "(FAIL|DONE)"
-> 536155.0 ns 26798: DONE
-> real 0m1.714s user 0m1.704s sys 0m0.044s
-> real 0m01.714s user 0m01.704s sys 0m00.044s
- w11a core test (using behavioural model)
@@ -112,7 +112,7 @@ Guide to running w11a test benches
time tbw tb_pdp11core |\
tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
-> 1220255.0 ns 61003: DONE
-> real 0m10.736s user 0m10.713s sys 0m0.060s
-> real 0m10.736s user 0m10.713s sys 0m00.060s
- w11a core test (using post-synthesis model)
@@ -120,7 +120,7 @@ Guide to running w11a test benches
time tbw tb_pdp11core_ssim |\
tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
-> 1220255.0 ns 61003: DONE
-> real 1m9.738s user 1m9.588s sys 0m0.096s
-> real 1m09.738s user 1m09.588s sys 0m00.096s
3. System tests benches ---------------------------------------------------
@@ -177,7 +177,7 @@ Guide to running w11a test benches
@../../../../w11a/tb/tb_pdp11core_stim.dat |\
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 7757655.0 ns 387873: DONE
-> real 0m49.835s user 0m50.203s sys 0m0.696s
-> real 0m49.835s user 0m50.203s sys 0m00.696s
- sys_w11a_n2 test bench
@@ -188,4 +188,4 @@ Guide to running w11a test benches
@../../../../w11a/tb/tb_pdp11core_stim.dat |\
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 6673237.2 ns 387035: DONE
-> real 0m56.173s user 0m56.612s sys 0m0.604s
-> real 0m56.173s user 0m56.612s sys 0m00.604s

61
rtl/bplib/atlys/atlys_pins.ucf Normal file
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@@ -0,0 +1,61 @@
## $Id: atlys_pins.ucf 414 2011-10-11 19:38:12Z mueller $
##
## Pin locks for Atlys core functionality
## - USB UART
## - human I/O (switches, buttons, leds)
##
## Revision History:
## Date Rev Version Comment
## 2011-10-10 413 1.0.2 new BTN sequence: clockwise(U-R-D-L) - mid - reset
## 2011-08-05 403 1.0.1 Fix IOSTANDARD typos; rename _GPIO_ to _HIO_
## 2011-08-04 402 1.0 Initial version
##
## Notes:
## - Bank 0+1 are 3V3; Bank 2 switchable 3V3 or 2V5; Bank 3 is 1V8 (DDR mem)
## - default is DRIVE=12 | SLEW=SLOW
## - pin names from Digilent master AtlysGeneralUCF.zip are given as comments
##
## clocks --------------------------------------------------------------------
## AtlysGeneralUCF: clk
##
NET "I_CLK100" LOC = "l15" | IOSTANDARD=LVCMOS25;
##
## USB UART interface --------------------------------------------------------
## AtlysGeneralUCF: UartRx, UartTx (crossed!)
##
NET "I_USB_RXD" LOC = "a16" | IOSTANDARD=LVCMOS33;
NET "O_USB_TXD" LOC = "b16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
##
## SWIs ----------------------------------------------------------------------
## AtlysGeneralUCF: sw<0:7>
##
NET "I_HIO_SWI<0>" LOC = "a10" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<1>" LOC = "d14" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<2>" LOC = "c14" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<3>" LOC = "p15" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<4>" LOC = "p12" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<5>" LOC = "r5" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<6>" LOC = "t5" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<7>" LOC = "e4" | IOSTANDARD=LVCMOS33;
##
## BTNs ----------------------------------------------------------------------
## AtlysGeneralUCF: btn<0:5>; clockwise(U-R-D-L) - middle - reset
##
NET "I_HIO_BTN<0>" LOC = "n4" | IOSTANDARD=LVCMOS18; # BTNU
NET "I_HIO_BTN<1>" LOC = "f6" | IOSTANDARD=LVCMOS18; # BTNR
NET "I_HIO_BTN<2>" LOC = "p3" | IOSTANDARD=LVCMOS18; # BTND
NET "I_HIO_BTN<3>" LOC = "p4" | IOSTANDARD=LVCMOS18; # BTNL
NET "I_HIO_BTN<4>" LOC = "f5" | IOSTANDARD=LVCMOS18; # BTNC
NET "I_HIO_BTN<5>" LOC = "t15" | IOSTANDARD=LVCMOS18; # RESET (act.low!!)
##
## LEDs ----------------------------------------------------------------------
## AtlysGeneralUCF: Led<0:7>
##
NET "O_HIO_LED<0>" LOC = "u18" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<1>" LOC = "m14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<2>" LOC = "n14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<3>" LOC = "l14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<4>" LOC = "m13" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<5>" LOC = "d4" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<6>" LOC = "p16" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<7>" LOC = "n12" | IOSTANDARD=LVCMOS33;

23
rtl/bplib/atlys/atlys_pins_pma0_rs232.ucf Normal file
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@@ -0,0 +1,23 @@
## $Id: atlys_pins_pma0_rs232.ucf 403 2011-08-06 17:36:22Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-08-06 403 1.0 Initial version
##
## Pmod connector A top / usage RS232 for FTDI USB serport -------------------
##
## front view (towards PCB edge):
##
## P-6 P-1
## | |
## +-------------------------+
## | VCC GND TXD RXD CTS RTS |
## | VCC GND ... ... ... ... |
## =============================
## < HDMI connector>
##
##
NET "O_FUSP_RTS_N" LOC = "t3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
NET "I_FUSP_CTS_N" LOC = "r3" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "I_FUSP_RXD" LOC = "p6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "O_FUSP_TXD" LOC = "n5" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;

25
rtl/bplib/atlys/atlys_pins_pmod.ucf Normal file
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@@ -0,0 +1,25 @@
## $Id: atlys_pins_pmod.ucf 403 2011-08-06 17:36:22Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-08-06 403 1.0 Initial version
##
## Pmod connectors -----------------------------------------------------------
##
## front view (towards PCB edge):
##
## +-------------------------+
## | VCC GND P-4 P-3 P-2 P-1 |
## | VCC GND P10 P-9 P-8 P-7 |
## =============================
## < HDMI connector>
##
## Pmod A (top: 0-3; bot: 4-7; all 8 shared with HDMI Type D connector...)
NET "IO_PMODA<0>" LOC = "t3" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<1>" LOC = "r3" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<2>" LOC = "p6" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<3>" LOC = "n5" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<4>" LOC = "v9" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<5>" LOC = "t9" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<6>" LOC = "v4" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<7>" LOC = "t4" | IOSTANDARD=LVCMOS33;

7
rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_rs232_2l4l_iob.vhd 406 2011-08-14 21:06:44Z mueller $
-- $Id: bp_rs232_2l4l_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -36,7 +36,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.bpgenlib.all;
@@ -123,7 +122,7 @@ begin
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
@@ -155,7 +154,7 @@ begin
proc_regs_mux: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';

3
rtl/bplib/bpgen/bp_rs232_2line_iob.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_rs232_2line_iob.vhd 387 2011-07-03 17:24:52Z mueller $
-- $Id: bp_rs232_2line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,7 +32,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

3
rtl/bplib/bpgen/bp_rs232_4line_iob.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_rs232_4line_iob.vhd 391 2011-07-09 17:25:02Z mueller $
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,7 +32,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

3
rtl/bplib/bpgen/bp_swibtnled.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_swibtnled.vhd 403 2011-08-06 17:36:22Z mueller $
-- $Id: bp_swibtnled.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,7 +32,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

28
rtl/bplib/bpgen/bpgenlib.vhd
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@@ -1,4 +1,4 @@
-- $Id: bpgenlib.vhd 404 2011-08-07 22:00:25Z mueller $
-- $Id: bpgenlib.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,8 @@
-- Tool versions: 12.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-16 426 1.0.6 now numeric_std clean
-- 2011-10-10 413 1.0.5 add sn_humanio_demu
-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
@@ -28,7 +30,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
@@ -104,7 +106,7 @@ component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -153,11 +155,29 @@ component sn_humanio is -- human i/o handling: swi,btn,led,dsp
);
end component;
component sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

23
rtl/bplib/bpgen/sn_4x7segctl.vhd
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@@ -1,4 +1,4 @@
-- $Id: sn_4x7segctl.vhd 400 2011-07-31 09:02:16Z mueller $
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,9 +18,10 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
@@ -32,7 +33,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -51,12 +52,12 @@ end sn_4x7segctl;
architecture syn of sn_4x7segctl is
type regs_type is record
cdiv : std_logic_vector(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
end record regs_type;
constant regs_init : regs_type := (
conv_std_logic_vector(0,CDWIDTH),
slv(to_unsigned(0,CDWIDTH)),
(others=>'0')
);
@@ -93,7 +94,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
@@ -113,9 +114,9 @@ begin
r := R_REGS;
n := R_REGS;
n.cdiv := unsigned(r.cdiv) - 1;
n.cdiv := slv(unsigned(r.cdiv) - 1);
if unsigned(r.cdiv) = 0 then
n.dcnt := unsigned(r.dcnt) + 1;
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
chex := "0000";
@@ -142,13 +143,13 @@ begin
cano := "1111";
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(conv_integer(unsigned(r.dcnt))) := '0';
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(conv_integer(unsigned(chex))));
SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex))));
end process proc_next;

1
rtl/bplib/bpgen/sn_humanio.vbom
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@@ -2,7 +2,6 @@
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
bpgenlib.vbom
## sys_conf : sys_conf.vhd
# components
../../vlib/xlib/iob_reg_o_gen.vbom
bp_swibtnled.vbom

6
rtl/bplib/bpgen/sn_humanio.vhd
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@@ -1,4 +1,4 @@
-- $Id: sn_humanio.vhd 403 2011-08-06 17:36:22Z mueller $
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,10 +22,11 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
@@ -42,7 +43,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

7
rtl/bplib/bpgen/sn_humanio_demu.vbom Normal file
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@@ -0,0 +1,7 @@
# libs
../../vlib/slvtypes.vhd
bpgenlib.vbom
# components
bp_swibtnled.vbom
# design
sn_humanio_demu.vhd

195
rtl/bplib/bpgen/sn_humanio_demu.vhd Normal file
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@@ -0,0 +1,195 @@
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_demu - syn
-- Description: All BTN, SWI, LED handling for atlys
--
-- Dependencies: bpgen/bp_swibtnled
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
-- 2011-10-10 413 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end sn_humanio_demu;
architecture syn of sn_humanio_demu is
constant c_mode_led : slv2 := "00";
constant c_mode_dp : slv2 := "01";
constant c_mode_datl : slv2 := "10";
constant c_mode_dath : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
cnt : slv9; -- msec counter
up_1 : slbit; -- btn up last cycle
dn_1 : slbit; -- btn dn last cycle
led : slv8; -- led state
end record regs_type;
constant regs_init : regs_type := (
c_mode_led, -- mode
(others=>'0'), -- cnt
'0','0', -- up_1, dn_1
(others=>'0') -- led
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN_HW : slv6 := (others=>'0');
signal LED_HW : slv8 := (others=>'0');
begin
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
BWIDTH => 6,
LWIDTH => 8,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN_HW,
LED => LED_HW,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibtn : slv4 := (others=>'0');
variable iup : slbit := '0';
variable idn : slbit := '0';
variable ipuls : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
ibtn(1) := BTN_HW(1);
ibtn(2) := BTN_HW(4);
ibtn(3) := BTN_HW(3);
iup := BTN_HW(0);
idn := BTN_HW(2);
ipuls := '0';
n.up_1 := iup;
n.dn_1 := idn;
if iup='0' and idn='0' then
n.cnt := (others=>'0');
else
if CE_MSEC = '1' then
n.cnt := slv(unsigned(r.cnt) + 1);
if r.cnt = "111111111" then
ipuls := '1';
end if;
end if;
end if;
if iup='1' or idn='1' then
n.led := (others=>'0');
case r.mode is
when c_mode_led => n.led(0) := '1';
when c_mode_dp => n.led(1) := '1';
when c_mode_datl => n.led(2) := '1';
when c_mode_dath => n.led(3) := '1';
when others => null;
end case;
if iup='1' and (r.up_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) + 1);
elsif idn='1' and (r.dn_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) - 1);
end if;
else
case r.mode is
when c_mode_led => n.led := LED;
when c_mode_dp => n.led := "0000" & DSP_DP;
when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
when c_mode_dath => n.led := DSP_DAT(15 downto 8);
when others => null;
end case;
end if;
N_REGS <= n;
BTN <= ibtn;
LED_HW <= r.led;
end process proc_next;
end syn;

11
rtl/bplib/bpgen/sn_humanio_rbus.vhd
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@@ -1,4 +1,4 @@
-- $Id: sn_humanio_rbus.vhd 406 2011-08-14 21:06:44Z mueller $
-- $Id: sn_humanio_rbus.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus
-- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff
-- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic
@@ -65,7 +66,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
@@ -77,7 +78,7 @@ entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -183,7 +184,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else

21
rtl/bplib/issi/is61lv25616al.vhd
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@@ -1,6 +1,6 @@
-- $Id: is61lv25616al.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -21,9 +21,10 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
------------------------------------------------------------------------------
@@ -42,7 +43,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -108,7 +109,7 @@ end sim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -152,14 +153,14 @@ begin
variable ram : ram_type := (others=>datzero);
begin
if WE_EFF'event and WE_EFF='0' then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(conv_integer(unsigned(ADDR))) := to_x01(DATA);
if falling_edge(WE_EFF) then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
end if;
if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
DATA <= ram(conv_integer(unsigned(ADDR)));
DATA <= ram(to_integer(unsigned(ADDR)));
else
DATA <= (others=>'Z');
end if;

21
rtl/bplib/micron/mt45w8mw16b.vhd
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@@ -1,6 +1,6 @@
-- $Id: mt45w8mw16b.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,9 +23,10 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.3.2 now numeric_std clean
-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
-- 2010-06-03 298 1.3 add timing model again
-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
@@ -56,7 +57,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -170,7 +171,7 @@ begin
end if;
addr_last := L_ADDR;
end if;
if OE'event and OE='1' then
if rising_edge(OE) then
DOUT_VAL_OE <= '0', '1' after T_oe;
end if;
end process proc_dout_val;
@@ -203,14 +204,14 @@ begin
-- end of write cycle
-- note: to_x01 used below to prevent that 'z' a written into mem.
if WE_L_EFF'event and WE_L_EFF='0' then
ram(conv_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
if falling_edge(WE_L_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
end if;
if WE_U_EFF'event and WE_U_EFF='0' then
ram(conv_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
if falling_edge(WE_U_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
end if;
DOUT <= ram(conv_integer(unsigned(L_ADDR)));
DOUT <= ram(to_integer(unsigned(L_ADDR)));
end process proc_cram;

3
rtl/bplib/nexys2/n2_cram_dummy.vhd
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@@ -1,4 +1,4 @@
-- $Id: n2_cram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: n2_cram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,7 +27,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;

23
rtl/bplib/nexys2/n2_cram_memctl_as.vhd
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@@ -1,6 +1,6 @@
-- $Id: n2_cram_memctl_as.vhd 340 2010-11-27 13:00:57Z mueller $
-- $Id: n2_cram_memctl_as.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -21,7 +21,7 @@
-- Test bench: tb/tb_n2_cram_memctl
-- fw_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.5 now numeric_std clean
-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
-- cycle;
@@ -111,7 +112,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
@@ -304,7 +305,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
@@ -391,7 +392,7 @@ begin
idata_oe := '0';
if unsigned(r.cntdly) /= 0 then
n.cntdly := unsigned(r.cntdly) - 1;
n.cntdly := slv(unsigned(r.cntdly) - 1);
end if;
case r.state is
@@ -406,7 +407,7 @@ begin
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
n.cntdly:= conv_std_logic_vector(READ0DELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
n.state := s_rdwait0; -- next: wait
when s_rdwait0 => -- s_rdwait0: read wait low word
@@ -426,7 +427,7 @@ begin
idata_cei := '1'; -- latch input data
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
n.cntdly:= conv_std_logic_vector(READ1DELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
n.state := s_rdwait1; -- next: wait high word
when s_rdwait1 => -- s_rdwait1: read wait high word
@@ -461,7 +462,7 @@ begin
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.state := s_wrwait0; -- next: wait
when s_wrwait0 => -- s_rdput0: write wait 1st word
@@ -504,7 +505,7 @@ begin
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.state := s_wrwait1; -- next: wait
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
@@ -540,7 +541,7 @@ begin
if unsigned(r.cntce) >= 127 then -- if max ce count expired
n.fidle := '1'; -- set forced idle flag
else -- if max ce count not yet reached
n.cntce := unsigned(r.cntce) + 1; -- increment counter
n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
end if;
end if;

13
rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
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@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_core.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tb_nexys2_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,15 +20,16 @@
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -59,8 +60,8 @@ architecture sim of tb_nexys2_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8);
constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8);
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin

13
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
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@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: tb_nexys2_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,10 +23,11 @@
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
@@ -35,7 +36,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -100,7 +101,7 @@ architecture sim of tb_nexys2_fusp is
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 20 ns;
constant clockosc_offset : time := 200 ns;
@@ -215,7 +216,7 @@ begin
begin
loop
wait until CLKSYS'event and CLKSYS='1';
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then

3
rtl/bplib/s3board/s3_sram_dummy.vhd
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@@ -1,4 +1,4 @@
-- $Id: s3_sram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,7 +28,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;

11
rtl/bplib/s3board/s3_sram_memctl.vhd
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@@ -1,6 +1,6 @@
-- $Id: s3_sram_memctl.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -21,7 +21,7 @@
-- Test bench: tb/tb_s3_sram_memctl
-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.6 now numeric_std clean
-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface
@@ -76,7 +77,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
@@ -213,7 +214,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else

3
rtl/bplib/s3board/s3boardlib.vhd
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@@ -1,4 +1,4 @@
-- $Id: s3boardlib.vhd 391 2011-07-09 17:25:02Z mueller $
-- $Id: s3boardlib.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -41,7 +41,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;

13
rtl/bplib/s3board/tb/tb_s3board_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_s3board_core.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tb_s3board_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,16 +20,17 @@
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -55,8 +56,8 @@ architecture sim of tb_s3board_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8);
constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8);
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin

13
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
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@@ -1,6 +1,6 @@
-- $Id: tb_s3board_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: tb_s3board_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,9 +23,10 @@
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
@@ -36,7 +37,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -95,7 +96,7 @@ architecture sim of tb_s3board_fusp is
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
@@ -198,7 +199,7 @@ begin
begin
loop
wait until CLK'event and CLK='1';
wait until rising_edge(CLK);
wait for c2out_time;
if RXERR = '1' then

75
rtl/ibus/ib_intmap.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ib_intmap.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ib_intmap.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,10 @@
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
@@ -31,7 +32,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -58,41 +59,41 @@ architecture syn of ib_intmap is
type intv_type is array (15 downto 0) of slv9;
constant conf_intp : intp_type :=
(conv_std_logic_vector(INTMAP(15).pri,3), -- line 15
conv_std_logic_vector(INTMAP(14).pri,3), -- line 14
conv_std_logic_vector(INTMAP(13).pri,3), -- line 13
conv_std_logic_vector(INTMAP(12).pri,3), -- line 12
conv_std_logic_vector(INTMAP(11).pri,3), -- line 11
conv_std_logic_vector(INTMAP(10).pri,3), -- line 10
conv_std_logic_vector(INTMAP( 9).pri,3), -- line 9
conv_std_logic_vector(INTMAP( 8).pri,3), -- line 8
conv_std_logic_vector(INTMAP( 7).pri,3), -- line 7
conv_std_logic_vector(INTMAP( 6).pri,3), -- line 6
conv_std_logic_vector(INTMAP( 5).pri,3), -- line 5
conv_std_logic_vector(INTMAP( 4).pri,3), -- line 4
conv_std_logic_vector(INTMAP( 3).pri,3), -- line 3
conv_std_logic_vector(INTMAP( 2).pri,3), -- line 2
conv_std_logic_vector(INTMAP( 1).pri,3), -- line 1
conv_std_logic_vector( 0,3) -- line 0 (always 0 !!)
(slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
);
constant conf_intv : intv_type :=
(conv_std_logic_vector(INTMAP(15).vec,9), -- line 15
conv_std_logic_vector(INTMAP(14).vec,9), -- line 14
conv_std_logic_vector(INTMAP(13).vec,9), -- line 13
conv_std_logic_vector(INTMAP(12).vec,9), -- line 12
conv_std_logic_vector(INTMAP(11).vec,9), -- line 11
conv_std_logic_vector(INTMAP(10).vec,9), -- line 10
conv_std_logic_vector(INTMAP( 9).vec,9), -- line 9
conv_std_logic_vector(INTMAP( 8).vec,9), -- line 8
conv_std_logic_vector(INTMAP( 7).vec,9), -- line 7
conv_std_logic_vector(INTMAP( 6).vec,9), -- line 6
conv_std_logic_vector(INTMAP( 5).vec,9), -- line 5
conv_std_logic_vector(INTMAP( 4).vec,9), -- line 4
conv_std_logic_vector(INTMAP( 3).vec,9), -- line 3
conv_std_logic_vector(INTMAP( 2).vec,9), -- line 2
conv_std_logic_vector(INTMAP( 1).vec,9), -- line 1
conv_std_logic_vector( 0,9) -- line 0 (always 0 !!)
(slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
);
-- attribute PRIORITY_EXTRACT : string;
@@ -122,7 +123,7 @@ begin
variable iei_ack : slv16 := (others=>'0');
begin
iline := conv_integer(unsigned(EI_LINE));
iline := to_integer(unsigned(EI_LINE));
iei_ack := (others=>'0');
if EI_ACKM = '1' then

4
rtl/ibus/ib_sel.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ib_sel.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ib_sel.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -54,7 +54,7 @@ begin
proc_regs: process (CLK)
variable isel : slbit := '0';
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
isel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto SAWIDTH+1)=IB_ADDR(12 downto SAWIDTH+1) then

25
rtl/ibus/ibd_iist.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibd_iist.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -29,6 +29,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
-- also for dcf_dcf and exc_rte; add iist_mreq and
@@ -40,7 +41,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -69,7 +70,7 @@ end ibd_iist;
architecture syn of ibd_iist is
constant ibaddr_iist : slv16 := conv_std_logic_vector(8#177500#,16);
constant ibaddr_iist : slv16 := slv(to_unsigned(8#177500#,16));
constant tdlysnd : natural := 150; -- send delay timer
@@ -223,7 +224,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if BRESET = '1' or -- BRESET is 1 for system and ibus reset
R_REGS.req_clear='1' then
R_REGS <= regs_init; --
@@ -280,14 +281,14 @@ begin
tcnt256_end := '0';
if CE_USEC='1' and r.stc_enb='1'then -- if st enabled on every usec
n.tcnt256 := unsigned(r.tcnt256) + 1; -- advance 8 bit counter
n.tcnt256 := slv(unsigned(r.tcnt256) + 1); -- advance 8 bit counter
if unsigned(r.tcnt256) = 255 then -- if wrap
tcnt256_end := '1'; -- signal 256 usec passed
end if;
end if;
tcntsnd_end := '0';
n.tcntsnd := unsigned(r.tcntsnd) + 1; -- advance send timer counter
n.tcntsnd := slv(unsigned(r.tcntsnd) + 1); -- advance send timer counter
if unsigned(r.tcntsnd) = tdlysnd-1 then -- if delay time reached
tcntsnd_end := '1'; -- signal end
end if;
@@ -559,7 +560,7 @@ begin
if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10
if IB_MREQ.rmw = '0' then -- if not 1st part of rmw
n.acr_ac := unsigned(r.acr_ac) + 1; -- autoincrement
n.acr_ac := slv(unsigned(r.acr_ac) + 1); -- autoincrement
end if;
end if;
@@ -570,7 +571,7 @@ begin
-- sanity timer
if tcnt256_end = '1' then -- if 256 usec expired (and enabled)
n.stc_count := unsigned(r.stc_count) - 1;
n.stc_count := slv(unsigned(r.stc_count) - 1);
if unsigned(r.stc_count) = 0 then -- if sanity timer expired
n.stc_tmo := '1'; -- set timeout flag
n.req_stsnd := '1'; -- request st transmit
@@ -598,8 +599,8 @@ begin
eff_bus(i).bmask(2) xor eff_bus(i).bmask(3) xor
not eff_bus(i).par;
act_ibit := eff_bus(i).imask(conv_integer(unsigned(eff_id)));
act_bbit := eff_bus(i).bmask(conv_integer(unsigned(eff_id)));
act_ibit := eff_bus(i).imask(to_integer(unsigned(eff_id)));
act_bbit := eff_bus(i).bmask(to_integer(unsigned(eff_id)));
n.dcf_brk(i) := eff_bus(i).dcf; -- trace dcf state in brk

15
rtl/ibus/ibd_kw11l.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibd_kw11l.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibd_kw11l.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
@@ -38,7 +39,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -60,7 +61,7 @@ end ibd_kw11l;
architecture syn of ibd_kw11l is
constant ibaddr_kw11l : slv16 := conv_std_logic_vector(8#177546#,16);
constant ibaddr_kw11l : slv16 := slv(to_unsigned(8#177546#,16));
constant lks_ibf_ie : integer := 6;
constant lks_ibf_moni : integer := 7;
@@ -91,7 +92,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
@@ -142,7 +143,7 @@ begin
-- other state changes
if CE_MSEC = '1' then
n.tcnt := unsigned(r.tcnt) + 1;
n.tcnt := slv(unsigned(r.tcnt) + 1);
if unsigned(r.tcnt) = tdivide-1 then
n.tcnt := (others=>'0');
n.moni := '1';

19
rtl/ibus/ibdlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdlib.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Definitions for ibus devices
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys
@@ -31,7 +32,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -67,6 +68,12 @@ end record iist_sres_type;
constant iist_sres_init : iist_sres_type := ('0','0');
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.
constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16));
constant ibaddr_dl11 : slv16 := slv(to_unsigned(8#177560#,16));
component ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
@@ -158,7 +165,7 @@ end component;
component ibdr_dz11 is -- ibus dev(rem): DZ11
generic (
IB_ADDR : slv16 := conv_std_logic_vector(8#160100#,16));
IB_ADDR : slv16 := ibaddr_dz11);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
@@ -175,7 +182,7 @@ end component;
component ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := conv_std_logic_vector(8#177560#,16));
IB_ADDR : slv16 := ibaddr_dl11);
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse

15
rtl/ibus/ibdr_dl11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_dl11.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
@@ -44,7 +45,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -52,7 +53,7 @@ use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := conv_std_logic_vector(8#177560#,16));
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
@@ -123,7 +124,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
@@ -311,7 +312,7 @@ begin
n.rdlybsy := '1'; -- set busy
end if;
elsif CE_USEC = '1' then -- if end-of-usec
n.rdlycnt := unsigned(r.rdlycnt) - 1; -- decrement
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement
if r.rdlybsy='1' and -- if delay busy
unsigned(r.rdlycnt) = 0 then -- and counter at zero
n.rdlybsy := '0'; -- clear busy

13
rtl/ibus/ibdr_lp11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_lp11.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_lp11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
@@ -42,7 +43,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -64,7 +65,7 @@ end ibdr_lp11;
architecture syn of ibdr_lp11 is
constant ibaddr_lp11 : slv16 := conv_std_logic_vector(8#177514#,16);
constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16));
constant ibaddr_csr : slv1 := "0"; -- csr address offset
constant ibaddr_buf : slv1 := "1"; -- buf address offset
@@ -99,7 +100,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset

11
rtl/ibus/ibdr_maxisys.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_maxisys.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_maxisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -27,7 +27,7 @@
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -36,6 +36,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11
@@ -72,7 +73,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -265,7 +266,7 @@ begin
begin
I0 : ibdr_dl11
generic map (
IB_ADDR => conv_std_logic_vector(8#176500#,16))
IB_ADDR => slv(to_unsigned(8#176500#,16)))
port map (
CLK => CLK,
CE_USEC => CE_USEC,

9
rtl/ibus/ibdr_minisys.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_minisys.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,7 +23,7 @@
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -32,6 +32,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
@@ -58,7 +59,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;

13
rtl/ibus/ibdr_pc11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_pc11.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_pc11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
@@ -37,7 +38,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -61,7 +62,7 @@ end ibdr_pc11;
architecture syn of ibdr_pc11 is
constant ibaddr_pc11 : slv16 := conv_std_logic_vector(8#177550#,16);
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
@@ -116,7 +117,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset

23
rtl/ibus/ibdr_rk11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_rk11.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
@@ -48,7 +49,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
@@ -71,7 +72,7 @@ end ibdr_rk11;
architecture syn of ibdr_rk11 is
constant ibaddr_rk11 : slv16 := conv_std_logic_vector(8#177400#,16);
constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
constant ibaddr_rker : slv3 := "001"; -- rker address offset
@@ -190,7 +191,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if BRESET='1' or R_REGS.creset='1' then
R_REGS <= regs_init;
if R_REGS.creset = '1' then
@@ -262,7 +263,7 @@ begin
when s_init =>
ibhold := r.ibsel; -- hold ibus when controller busy
icrip := '1';
n.icnt := unsigned(r.icnt) + 1;
n.icnt := slv(unsigned(r.icnt) + 1);
if unsigned(r.icnt) = 7 then
n.state := s_idle;
end if;
@@ -296,7 +297,7 @@ begin
idout(rkds_ibf_sc) := r.sc;
end if;
if r.sbusy(conv_integer(unsigned(imem_addr(2 downto 0))))='1' then
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
end if;
@@ -359,7 +360,7 @@ begin
if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek
unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset
n.sbusy(conv_integer(unsigned(r.drsel))) := '1'; -- set busy
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy
end if;
end if;
@@ -441,7 +442,7 @@ begin
elsif iscval = '1' then -- was a seek done
n.scp := '1'; -- signal seek complete interrupt
n.id := iscid; -- load id
n.sireq(conv_integer(unsigned(iscid))) := '0'; -- reset sireq bit
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
end if;
end if;
@@ -456,7 +457,7 @@ begin
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
n.sc := (others=>'0');
else
n.sc := unsigned(r.sc) + 1;
n.sc := slv(unsigned(r.sc) + 1);
end if;
end if;

13
rtl/ibus/ibdr_sdreg.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_sdreg.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_sdreg.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.1 now numeric_std clean
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2008-08-22 161 1.0.4 use iblib
@@ -40,7 +41,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
@@ -59,7 +60,7 @@ end ibdr_sdreg;
architecture syn of ibdr_sdreg is
constant ibaddr_sdreg : slv16 := conv_std_logic_vector(8#177570#,16);
constant ibaddr_sdreg : slv16 := slv(to_unsigned(8#177570#,16));
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
@@ -80,7 +81,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else

3
rtl/ibus/iblib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: iblib.vhd 346 2010-12-22 22:59:26Z mueller $
-- $Id: iblib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,7 +28,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;

7
rtl/sys_gen/tst_rlink/nexys2/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -18,11 +18,6 @@ all : $(BIT_all)
clean : ise_clean
rm -f sys_tst_rlink_n2.ucf
#
sys_tst_rlink_n2.mcs : sys_tst_rlink_n2.bit
promgen -w -x xcf04s -p mcs -u 0 sys_tst_rlink_n2
mv sys_tst_rlink_n2.prm sys_tst_rlink_n2_prm.log
mv sys_tst_rlink_n2.cfi sys_tst_rlink_n2_cfi.log
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk

4
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_tst_rlink_n2.mfset 406 2011-08-14 21:06:44Z mueller $
# $Id: sys_tst_rlink_n2.mfset 427 2011-11-19 21:04:11Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
@@ -9,7 +9,7 @@ Node <HIO/R_REGS.swi_[1-7]> of sequential type is unconnected
Node <HIO/R_REGS.btneff_[0-5]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-5]> of sequential type is unconnected
Unconnected output port 'LOCKED' of component 'dcm_sp_sfs'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'

4
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom
View File

@@ -8,8 +8,8 @@
../../../bplib/nexys2/nexys2lib.vhd
sys_conf : sys_conf.vhd
# components
[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom

10
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_rlink_n2.vhd 406 2011-08-14 21:06:44Z mueller $
-- $Id: sys_tst_rlink_n2.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,7 +15,7 @@
-- Module Name: sys_tst_rlink_n2 - syn
-- Description: rlink tester design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sp_sfs
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
@@ -25,7 +25,7 @@
-- Test bench: tb/tb_tst_rlink_n2
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -35,6 +35,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.1.3 use dcm_sfs now
-- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.1.1 use now sn_humanio
-- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level
@@ -60,7 +61,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;
@@ -137,7 +137,7 @@ begin
RESET <= '0'; -- so far not used
DCM : dcm_sp_sfs
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,

11
rtl/sys_gen/tst_rlink/tst_rlink.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tst_rlink.vhd 385 2011-06-26 22:10:57Z mueller $
-- $Id: tst_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,10 +26,11 @@
-- Test bench: nexys2/tb/tb_tst_rlink_n2
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.1.1 now numeric_std clean
-- 2011-06-26 385 1.1 remove s3_humanio_rbus (will be in board design);
-- remove hio interface ports, add rbus ports
-- 2011-04-02 375 1.0.1 add rbd_eyemon and two timer
@@ -42,7 +43,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
@@ -113,7 +114,7 @@ begin
OFAWIDTH => 0,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
RB_ADDR => conv_std_logic_vector(2#11111110#,8),
RB_ADDR => slv(to_unsigned(2#11111110#,8)),
CDWIDTH => 13,
CDINIT => CDINIT)
port map (
@@ -175,7 +176,7 @@ begin
EMON : rbd_eyemon
generic map (
RB_ADDR => rbaddr_emon,
RDIV => conv_std_logic_vector(0,8))
RDIV => slv(to_unsigned(0,8)))
port map (
CLK => CLK,
RESET => RESET,

23
rtl/sys_gen/tst_snhumanio/Makefile Normal file
View File

@@ -0,0 +1,23 @@
# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-09-17 410 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ISE_PATH = xc3s1000-ft256-4
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#

4
rtl/sys_gen/tst_snhumanio/atlys/.cvsignore Normal file
View File

@@ -0,0 +1,4 @@
_impactbatch.log
sys_tst_snhumanio_atlys.ucf
*.dep_ucf_cpp
*.svf

30
rtl/sys_gen/tst_snhumanio/atlys/Makefile Normal file
View File

@@ -0,0 +1,30 @@
# $Id: Makefile 414 2011-10-11 19:38:12Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-10-11 414 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = atlys
ISE_PATH = xc6slx45-csg324-2
#
XFLOWOPT_SYN = syn_s6_speed.opt
XFLOWOPT_IMP = imp_s6_speed.opt
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_atlys.ucf
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

35
rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd Normal file
View File

@@ -0,0 +1,35 @@
-- $Id: sys_conf.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_atlys (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;

29
rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset Normal file
View File

@@ -0,0 +1,29 @@
# $Id: sys_tst_snhumanio_atlys.mfset 416 2011-10-15 13:32:57Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Case statement is complete. others clause is never selected
sys_tst_snhumanio_atlys\..*Output port <CE_USEC> of the instance <CLKDIV> is unconnected
Node <CLKDIV/R_REGS_usec> of sequential type is unconnected
The FF/Latch <HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[0-1]> in Unit <.*> is equivalent
The small RAM <.*> will be implemented on LUTs
#
# ----------------------------------------------------------------------------
[tra]
#
# ----------------------------------------------------------------------------
[map]
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
#
# ----------------------------------------------------------------------------
[bgn]

16
rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp Normal file
View File

@@ -0,0 +1,16 @@
## $Id: sys_tst_snhumanio_atlys.ucf_cpp 414 2011-10-11 19:38:12Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-10-11 414 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## std board
##
#include "bplib/atlys/atlys_pins.ucf"
#include "bplib/atlys/atlys_pins_pma0_rs232.ucf"

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# libs
../../../vlib/slvtypes.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
sys_conf : sys_conf.vhd
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio_demu.vbom
../tst_snhumanio.vbom
# design
sys_tst_snhumanio_atlys.vhd
@ucf_cpp: sys_tst_snhumanio_atlys.ucf

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-- $Id: sys_tst_snhumanio_atlys.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_atlys - syn
-- Description: snhumanio tester design for atlys
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio_demu
-- tst_snhumanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-10-11 414 13.1 O40d xc6slx45 166 196 - 60 t 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Atlys Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_atlys is -- top level
-- implements xxx_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
-- O_CLKSYS : out slbit; -- DCM derived system clock
I_USB_RXD : in slbit; -- USB UART receive data (board view)
O_USB_TXD : out slbit; -- USB UART transmit data (board view)
I_HIO_SWI : in slv8; -- atlys hio switches
I_HIO_BTN : in slv6; -- atlys hio buttons
O_HIO_LED: out slv8; -- atlys hio leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_snhumanio_atlys;
architecture syn of sys_tst_snhumanio_atlys is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 100,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio_demu
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_HIO_SWI,
I_BTN => I_HIO_BTN,
O_LED => O_HIO_LED
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_USB_TXD <= I_USB_RXD;
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
end syn;

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_impactbatch.log
sys_tst_snhumanio_n2.ucf
*.dep_ucf_cpp
*.svf

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# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-09-17 410 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_n2.ucf
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

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rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd Normal file
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-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;

34
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# $Id: sys_tst_snhumanio_n2.mfset 412 2011-10-08 15:15:20Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'CE_USEC' of component 'clkdivce'
Input <I_MEM_WAIT> is never used
FF/Latch <R_REGS.ucnt_\d*> has a constant value of 0
Node <CLKDIV/R_REGS.usec> of sequential type is unconnected
#
# ----------------------------------------------------------------------------
[tra]
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete

15
rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp Normal file
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## $Id: sys_tst_snhumanio_n2.ucf_cpp 410 2011-09-18 11:23:09Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-09-17 410 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
## std board
##
#include "bplib/nexys2/nexys2_pins.ucf"

14
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nexys2/nexys2lib.vhd
sys_conf : sys_conf.vhd
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_snhumanio.vbom
../../../bplib/nexys2/n2_cram_dummy.vbom
# design
sys_tst_snhumanio_n2.vhd
@ucf_cpp: sys_tst_snhumanio_n2.ucf

159
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-- $Id: sys_tst_snhumanio_n2.vhd 419 2011-11-01 19:42:30Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n2 - syn
-- Description: snhumanio tester design for nexys2
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nexys2/n2_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nexys2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end sys_tst_snhumanio_n2;
architecture syn of sys_tst_snhumanio_n2 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_FLA_CE_N => O_FLA_CE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;

4
rtl/sys_gen/tst_snhumanio/s3board/.cvsignore Normal file
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_impactbatch.log
sys_tst_snhumanio_s3.ucf
*.dep_ucf_cpp
*.svf

27
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# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-09-18 410 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = s3board
ISE_PATH = xc3s1000-ft256-4
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_s3.ucf
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

35
rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd Normal file
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-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;

27
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# $Id: sys_tst_snhumanio_s3.mfset 417 2011-10-22 10:30:29Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'CE_USEC' of component 'clkdivce'
FF/Latch <R_REGS.ucnt_\d*> has a constant value of 0
Node <CLKDIV/R_REGS.usec> of sequential type is unconnected
#
# ----------------------------------------------------------------------------
[tra]
#
# ----------------------------------------------------------------------------
[map]
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
#
# ----------------------------------------------------------------------------
[bgn]

15
rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp Normal file
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## $Id: sys_tst_snhumanio_s3.ucf_cpp 410 2011-09-18 11:23:09Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-09-18 410 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
## std board
##
#include "bplib/s3board/s3board_pins.ucf"

14
rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/s3board/s3boardlib.vhd
sys_conf : sys_conf.vhd
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_snhumanio.vbom
../../../bplib/s3board/s3_sram_dummy.vbom
# design
sys_tst_snhumanio_s3.vhd
@ucf_cpp: sys_tst_snhumanio_s3.ucf

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-- $Id: sys_tst_snhumanio_s3.vhd 419 2011-11-01 19:42:30Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_s3 - syn
-- Description: snhumanio tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- s3board/s3_sram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-18 410 13.1 O40d xc3s1000-4 149 211 - 143 t 11.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-10-15 416 1.0.1 remove O_CLKSYS top level port
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_s3 is -- top level
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end sys_tst_snhumanio_s3;
architecture syn of sys_tst_snhumanio_s3 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;

6
rtl/sys_gen/tst_snhumanio/tst_snhumanio.vbom Normal file
View File

@@ -0,0 +1,6 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/comlib/comlib.vhd
# components
# design
tst_snhumanio.vhd

234
rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd Normal file
View File

@@ -0,0 +1,234 @@
-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_snhumanio - syn
-- Description: simple stand-alone tester for sn_humanio
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-15 416 1.0.2 fix sensitivity list of proc_next
-- 2011-10-08 412 1.0.1 use better rndm init (so that swi=0 is non-const)
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
-- ----------------------------------------------------------------------------
entity tst_snhumanio is -- tester for rlink
generic (
BWIDTH : positive := 4); -- BTN port width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
SWI : in slv8; -- switch settings
BTN : in slv(BWIDTH-1 downto 0); -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_snhumanio;
architecture syn of tst_snhumanio is
constant c_mode_rndm : slv2 := "00";
constant c_mode_cnt : slv2 := "01";
constant c_mode_swi : slv2 := "10";
constant c_mode_btst : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
allon : slbit; -- all LEDs on if set
cnt : slv16; -- counter
tcnt : slv16; -- swi/btn toggle counter
rndm : slv8; -- random number
swi_1 : slv8; -- last SWI state
btn_1 : slv(BWIDTH-1 downto 0); -- last BTN state
led : slv8; -- LED output state
dsp : slv16; -- display data
dp : slv4; -- display decimal points
end record regs_type;
-- the rndm start value is /= 0 because a seed of 0 with a SWI setting of 0
-- will result in a 0-0-0 sequence. The 01010101 start will get trapped in a
-- constant sequence with a 01100011 switch setting, which is rather unlikely.
constant rndminit : slv8 := "01010101";
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
c_mode_rndm, -- mode
'0', -- allon
(others=>'0'), -- cnt
(others=>'0'), -- tcnt
rndminit, -- rndm
(others=>'0'), -- swi_1
btnzero, -- btn_1
(others=>'0'), -- led
(others=>'0'), -- dsp
(others=>'0') -- dp
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN4 : slbit := '0';
begin
assert BWIDTH>=4
report "assert(BWIDTH>=4): at least 4 BTNs available"
severity failure;
B4YES: if BWIDTH > 4 generate
BTN4 <= BTN(4);
end generate B4YES;
B4NO: if BWIDTH = 4 generate
BTN4 <= '0';
end generate B4NO;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, SWI, BTN, BTN4)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable btn03 : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
n.swi_1 := SWI;
n.btn_1 := BTN;
if SWI/=r.swi_1 or BTN/=r.btn_1 then
n.tcnt := slv(unsigned(r.tcnt) + 1);
end if;
btn03 := BTN(3 downto 0);
n.allon := BTN4;
if unsigned(BTN) /= 0 then -- is a button being pressed ?
if r.mode /= c_mode_btst then -- not in btst mode
case btn03 is
when "0001" => -- 0001 single button -> rndm mode
n.mode := c_mode_rndm;
n.rndm := rndminit;
when "0010" => -- 0010 single button -> cnt mode
n.mode := c_mode_cnt;
when "0100" => -- 0100 single button -> swi mode
n.mode := c_mode_swi;
when "1000" => -- 1001 single button -> btst mode
n.mode := c_mode_btst;
n.tcnt := (others=>'0');
when others => -- any 2+ button combo -> led test
n.allon := '1';
end case;
else -- button press in btst mode
case btn03 is
when "1001" => -- 1001 double btn -> rndm mode
n.mode := c_mode_rndm;
when "1010" => -- 1010 double btn -> rndm cnt
n.mode := c_mode_cnt;
when "1100" => -- 1100 double btn -> rndm swi
n.mode := c_mode_swi;
when others => null;
end case;
end if;
else -- no button being pressed
if CE_MSEC = '1' then -- on every usec
n.cnt := slv(unsigned(r.cnt) + 1); -- inc counter
if unsigned(r.cnt(8 downto 0)) = 0 then -- every 1/2 sec (approx.)
n.rndm := crc8_update(r.rndm, SWI); -- update rndm state
end if;
end if;
end if;
if r.allon = '1' then -- if led test selected
n.led := (others=>'1'); -- all led,dsp,dp on
n.dsp := (others=>'1');
n.dp := (others=>'1');
else -- no led test, normal output
case r.mode is
when c_mode_rndm =>
n.led := r.rndm;
n.dsp(7 downto 0) := r.rndm;
n.dsp(15 downto 8) := not r.rndm;
when c_mode_cnt =>
n.led := r.cnt(14 downto 7);
n.dsp := r.cnt;
when c_mode_swi =>
n.led := SWI;
n.dsp(7 downto 0) := SWI;
n.dsp(15 downto 8) := not SWI;
when c_mode_btst =>
n.led := SWI;
n.dsp := r.tcnt;
when others => null;
end case;
n.dp := BTN(3 downto 0);
end if;
N_REGS <= n;
LED <= r.led;
DSP_DAT <= r.dsp;
DSP_DP <= r.dp;
end process proc_next;
end syn;

9
rtl/sys_gen/w11a/nexys2/sys_conf.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_conf.vhd 341 2010-11-27 23:05:43Z mueller $
-- $Id: sys_conf.vhd 428 2011-11-20 12:19:31Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Definitions for sys_w11a_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...)
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-05 295 1.0 Initial version (derived from _s3 version)
------------------------------------------------------------------------------
@@ -37,7 +38,7 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 25;
constant sys_conf_clkfx_multiply : positive := 29; -- ==> 58 MHz
constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;

4
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_n2.mfset 406 2011-08-14 21:06:44Z mueller $
# $Id: sys_w11a_n2.mfset 427 2011-11-19 21:04:11Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
@@ -14,7 +14,7 @@ Node <HIO/R_REGS.swi_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected
Node <MEM_SRAM.SRAM_CTL/R_REGS.addr0> of sequential type is unconnected
Unconnected output port 'LOCKED' of component 'dcm_sp_sfs'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'RL_MONI' of component 'rlink_base_serport'
Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport'
Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as'

4
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
View File

@@ -11,8 +11,8 @@
../../../w11a/pdp11.vhd
sys_conf = sys_conf.vhd
# components
[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom

13
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n2.vhd 404 2011-08-07 22:00:25Z mueller $
-- $Id: sys_w11a_n2.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,7 +15,7 @@
-- Module Name: sys_w11a_n2 - syn
-- Description: w11a test design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sp_sfs
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
@@ -36,10 +36,11 @@
-- Test bench: tb/tb_sys_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
@@ -62,6 +63,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.2.4 now numeric_std clean
-- 2011-11-17 426 1.2.3 use dcm_sfs now
-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.2.1 use now sn_humanio
-- 2010-12-30 351 1.2 ported to rbv3
@@ -111,7 +114,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
@@ -241,7 +244,7 @@ begin
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sp_sfs
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,

8
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_s3.vhd 404 2011-08-07 22:00:25Z mueller $
-- $Id: sys_w11a_s3.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -35,10 +35,11 @@
-- Test bench: tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II
@@ -71,6 +72,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.4.3 now numeric_std clean
-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.4.1 use now sn_humanio
-- 2010-12-30 351 1.4 ported to rbv3
@@ -129,7 +131,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;

11
rtl/vlib/comlib/byte2cdata.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: byte2cdata.vhd 348 2010-12-26 15:23:44Z mueller $
-- $Id: byte2cdata.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,17 +18,18 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -79,7 +80,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else

11
rtl/vlib/comlib/cdata2byte.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: cdata2byte.vhd 348 2010-12-26 15:23:44Z mueller $
-- $Id: cdata2byte.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,17 +18,18 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -81,7 +82,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else

113
rtl/vlib/comlib/comlib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: comlib.vhd 400 2011-07-31 09:02:16Z mueller $
-- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,9 +16,11 @@
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial
-- of Koopman et al.; crc8_update(_tbl) now function
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
@@ -29,7 +31,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -107,10 +109,8 @@ component crc8 is -- crc-8 generator, checker
);
end component;
procedure crc8_update (crc : inout slv8;
data : in slv8);
procedure crc8_update_tbl (crc : inout slv8;
data : in slv8);
function crc8_update (crc : in slv8; data : in slv8) return slv8;
function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8;
end package comlib;
@@ -118,67 +118,68 @@ end package comlib;
package body comlib is
procedure crc8_update (crc : inout slv8;
data : in slv8) is
function crc8_update (crc: in slv8; data: in slv8) return slv8 is
variable t : slv8 := (others=>'0');
variable n : slv8 := (others=>'0');
begin
t := data xor crc;
crc(0) := t(0) xor t(4) xor t(5) xor t(6);
crc(1) := t(1) xor t(5) xor t(6) xor t(7);
crc(2) := t(0) xor t(2) xor t(4) xor t(5) xor t(7);
crc(3) := t(0) xor t(1) xor t(3) xor t(4);
crc(4) := t(0) xor t(1) xor t(2) xor t(6);
crc(5) := t(1) xor t(2) xor t(3) xor t(7);
crc(6) := t(2) xor t(3) xor t(4);
crc(7) := t(3) xor t(4) xor t(5);
n(0) := t(5) xor t(4) xor t(2) xor t(0);
n(1) := t(6) xor t(5) xor t(3) xor t(1);
n(2) := t(7) xor t(6) xor t(5) xor t(0);
n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0);
n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1);
n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2);
n(6) := t(7) xor t(3) xor t(2) xor t(0);
n(7) := t(4) xor t(3) xor t(1);
return n;
end procedure crc8_update;
end function crc8_update;
procedure crc8_update_tbl (crc : inout slv8;
data : in slv8) is
function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 29, 58, 39, 116, 105, 78, 83,
232, 245, 210, 207, 156, 129, 166, 187,
205, 208, 247, 234, 185, 164, 131, 158,
37, 56, 31, 2, 81, 76, 107, 118,
135, 154, 189, 160, 243, 238, 201, 212,
111, 114, 85, 72, 27, 6, 33, 60,
74, 87, 112, 109, 62, 35, 4, 25,
162, 191, 152, 133, 214, 203, 236, 241,
19, 14, 41, 52, 103, 122, 93, 64,
251, 230, 193, 220, 143, 146, 181, 168,
222, 195, 228, 249, 170, 183, 144, 141,
54, 43, 12, 17, 66, 95, 120, 101,
148, 137, 174, 179, 224, 253, 218, 199,
124, 97, 70, 91, 8, 21, 50, 47,
89, 68, 99, 126, 45, 48, 23, 10,
177, 172, 139, 150, 197, 216, 255, 226,
38, 59, 28, 1, 82, 79, 104, 117,
206, 211, 244, 233, 186, 167, 128, 157,
235, 246, 209, 204, 159, 130, 165, 184,
3, 30, 57, 36, 119, 106, 77, 80,
161, 188, 155, 134, 213, 200, 239, 242,
73, 84, 115, 110, 61, 32, 7, 26,
108, 113, 86, 75, 24, 5, 34, 63,
132, 153, 190, 163, 240, 237, 202, 215,
53, 40, 15, 18, 65, 92, 123, 102,
221, 192, 231, 250, 169, 180, 147, 142,
248, 229, 194, 223, 140, 145, 182, 171,
16, 13, 42, 55, 100, 121, 94, 67,
178, 175, 136, 149, 198, 219, 252, 225,
90, 71, 96, 125, 46, 51, 20, 9,
127, 98, 69, 88, 11, 22, 49, 44,
151, 138, 173, 176, 227, 254, 217, 196
);
( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07
242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f
169, 228, 51, 126, 208, 157, 74, 7, -- 10-17
91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f
31, 82, 133, 200, 102, 43, 252, 177, -- 20-27
237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f
182, 251, 44, 97, 207, 130, 85, 24, -- 30-37
68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f
62, 115, 164, 233, 71, 10, 221, 144, -- 40-47
204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f
151, 218, 13, 64, 238, 163, 116, 57, -- 50-57
101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f
33, 108, 187, 246, 88, 21, 194, 143, -- 60-67
211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f
136, 197, 18, 95, 241, 188, 107, 38, -- 70-70
122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f
124, 49, 230, 171, 5, 72, 159, 210, -- 80-87
142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f
213, 152, 79, 2, 172, 225, 54, 123, -- 90-97
39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f
99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7
145, 220, 11, 70, 232, 165, 114, 63, -- a0-af
202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7
56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf
66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7
176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf
235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7
25, 84, 131, 206, 96, 45, 250, 183, -- d0-df
93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7
175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef
244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7
6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff
);
begin
crc := conv_std_logic_vector(
crc8_tbl(conv_integer(unsigned(data xor crc))), 8);
return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8));
end procedure crc8_update_tbl;
end function crc8_update_tbl;
end package body comlib;

61
rtl/vlib/comlib/crc8.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: crc8.vhd 406 2011-08-14 21:06:44Z mueller $
-- $Id: crc8.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,34 +13,35 @@
--
------------------------------------------------------------------------------
-- Module Name: crc8 - syn
-- Description: 8bit CRC generator, use CRC-8-SAE J1850 polynomial.
-- Based on CRC-8-SAE J1850 polynomial:
-- x^8 + x^4 + x^3 + x^2 + 1 (0x1d)
-- It is irreducible, and can be implemented with <= 54 xor's
-- Description: 8bit CRC generator, use 'A6' polynomial of Koopman and
-- Chakravarty. Has HD=3 for up to 247 bits and optimal HD=2
-- error detection for longer messages:
--
-- Notes: # XST synthesis for a Spartan-3 gives:
-- 1-bit xor2 : 11
-- 1-bit xor4 : 5
-- 1-bit xor5 : 1
-- Number of 4 input LUTs: 20
-- # Synthesis with crc8_update_tbl gives a lut-rom based table
-- design. Even though a 256x8 bit ROM is behind, the optimizer
-- gets it into 12 slices with 22 4 input LUTs, thus only
-- little larger than with xor's.
-- x^8 + x^6 + x^3 + x^2 + 1 (0xa6)
--
-- It is irreducible, and can be implemented with <= 37 xor's
-- This polynomial is described in
-- http://dx.doi.org/10.1109%2FDSN.2004.1311885
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 8 25 - 13 (A6 polynom)
-- 2011-09-17 409 13.1 O40d xc3s1200e-4 8 18 - 10 (SAE J1850)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 409 1.1 use now 'A6' polynomial of Koopman et al.
-- 2011-08-14 406 1.0.1 remove superfluous variable r
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.comlib.all;
@@ -59,40 +60,24 @@ end crc8;
architecture syn of crc8 is
signal R_CRC : slv8 := INIT; -- state registers
signal N_CRC : slv8 := INIT; -- next value state regs
begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_CRC <= INIT;
else
R_CRC <= N_CRC;
if ENA = '1' then
R_CRC <= crc8_update(R_CRC, DI);
end if;
end if;
end if;
end process proc_regs;
proc_next: process (R_CRC, DI, ENA)
variable n : slv8 := INIT;
begin
n := R_CRC;
if ENA = '1' then
crc8_update(n, DI);
end if;
N_CRC <= n;
CRC <= R_CRC;
end process proc_next;
CRC <= R_CRC;
end syn;

17
rtl/vlib/comlib/misc/gen_crc8_tbl.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: gen_crc8_tbl.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: gen_crc8_tbl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -15,18 +15,18 @@
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to print crc8 transition table
--
-- Dependencies: comlib/crc8_update (procedure)
-- Dependencies: comlib/crc8_update (function)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.slvtypes.all;
@@ -41,13 +41,14 @@ begin
process
variable crc : slv8 := (others=>'0');
variable dat : slv8 := (others=>'0');
variable nxt : slv8 := (others=>'0');
variable oline : line;
begin
for i in 0 to 255 loop
crc := (others=>'0');
dat := conv_std_logic_vector(i,8);
crc8_update(crc, dat);
write(oline, conv_integer(unsigned(crc)), right, 4);
dat := slv(to_unsigned(i,8));
nxt := crc8_update(crc, dat);
write(oline, to_integer(unsigned(nxt)), right, 4);
if i /= 255 then
write(oline, string'(","));
end if;

78
rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: gen_crc8_tbl_check.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: gen_crc8_tbl_check.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,19 +19,15 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 use now 'A6' polynomial of Koopman et al.
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;
--use work.slvtypes.all;
--use work.comlib.all;
entity gen_crc8_tbl_check is
end gen_crc8_tbl_check;
@@ -42,40 +38,40 @@ begin
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 29, 58, 39, 116, 105, 78, 83,
232, 245, 210, 207, 156, 129, 166, 187,
205, 208, 247, 234, 185, 164, 131, 158,
37, 56, 31, 2, 81, 76, 107, 118,
135, 154, 189, 160, 243, 238, 201, 212,
111, 114, 85, 72, 27, 6, 33, 60,
74, 87, 112, 109, 62, 35, 4, 25,
162, 191, 152, 133, 214, 203, 236, 241,
19, 14, 41, 52, 103, 122, 93, 64,
251, 230, 193, 220, 143, 146, 181, 168,
222, 195, 228, 249, 170, 183, 144, 141,
54, 43, 12, 17, 66, 95, 120, 101,
148, 137, 174, 179, 224, 253, 218, 199,
124, 97, 70, 91, 8, 21, 50, 47,
89, 68, 99, 126, 45, 48, 23, 10,
177, 172, 139, 150, 197, 216, 255, 226,
38, 59, 28, 1, 82, 79, 104, 117,
206, 211, 244, 233, 186, 167, 128, 157,
235, 246, 209, 204, 159, 130, 165, 184,
3, 30, 57, 36, 119, 106, 77, 80,
161, 188, 155, 134, 213, 200, 239, 242,
73, 84, 115, 110, 61, 32, 7, 26,
108, 113, 86, 75, 24, 5, 34, 63,
132, 153, 190, 163, 240, 237, 202, 215,
53, 40, 15, 18, 65, 92, 123, 102,
221, 192, 231, 250, 169, 180, 147, 142,
248, 229, 194, 223, 140, 145, 182, 171,
16, 13, 42, 55, 100, 121, 94, 67,
178, 175, 136, 149, 198, 219, 252, 225,
90, 71, 96, 125, 46, 51, 20, 9,
127, 98, 69, 88, 11, 22, 49, 44,
151, 138, 173, 176, 227, 254, 217, 196
);
( 0, 77, 154, 215, 121, 52, 227, 174,
242, 191, 104, 37, 139, 198, 17, 92,
169, 228, 51, 126, 208, 157, 74, 7,
91, 22, 193, 140, 34, 111, 184, 245,
31, 82, 133, 200, 102, 43, 252, 177,
237, 160, 119, 58, 148, 217, 14, 67,
182, 251, 44, 97, 207, 130, 85, 24,
68, 9, 222, 147, 61, 112, 167, 234,
62, 115, 164, 233, 71, 10, 221, 144,
204, 129, 86, 27, 181, 248, 47, 98,
151, 218, 13, 64, 238, 163, 116, 57,
101, 40, 255, 178, 28, 81, 134, 203,
33, 108, 187, 246, 88, 21, 194, 143,
211, 158, 73, 4, 170, 231, 48, 125,
136, 197, 18, 95, 241, 188, 107, 38,
122, 55, 224, 173, 3, 78, 153, 212,
124, 49, 230, 171, 5, 72, 159, 210,
142, 195, 20, 89, 247, 186, 109, 32,
213, 152, 79, 2, 172, 225, 54, 123,
39, 106, 189, 240, 94, 19, 196, 137,
99, 46, 249, 180, 26, 87, 128, 205,
145, 220, 11, 70, 232, 165, 114, 63,
202, 135, 80, 29, 179, 254, 41, 100,
56, 117, 162, 239, 65, 12, 219, 150,
66, 15, 216, 149, 59, 118, 161, 236,
176, 253, 42, 103, 201, 132, 83, 30,
235, 166, 113, 60, 146, 223, 8, 69,
25, 84, 131, 206, 96, 45, 250, 183,
93, 16, 199, 138, 36, 105, 190, 243,
175, 226, 53, 120, 214, 155, 76, 1,
244, 185, 110, 35, 141, 192, 23, 90,
6, 75, 156, 209, 127, 50, 229, 168
);
variable crc : integer := 0;
variable oline : line;

23
rtl/vlib/genlib/clkdivce.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: clkdivce.vhd 341 2010-11-27 23:05:43Z mueller $
-- $Id: clkdivce.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,10 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
@@ -28,7 +29,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -55,8 +56,8 @@ architecture syn of clkdivce is
end record regs_type;
constant regs_init : regs_type := (
conv_std_logic_vector(USECDIV-1,CDUWIDTH),
conv_std_logic_vector(MSECDIV-1,10),
slv(to_unsigned(USECDIV-1,CDUWIDTH)),
slv(to_unsigned(MSECDIV-1,10)),
'0','0'
);
@@ -73,7 +74,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
@@ -92,14 +93,14 @@ begin
n.usec := '0';
n.msec := '0';
n.ucnt := unsigned(r.ucnt) - 1;
n.ucnt := slv(unsigned(r.ucnt) - 1);
if unsigned(r.ucnt) = 0 then
n.usec := '1';
n.ucnt := conv_std_logic_vector(USECDIV-1,CDUWIDTH);
n.mcnt := unsigned(r.mcnt) - 1;
n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH));
n.mcnt := slv(unsigned(r.mcnt) - 1);
if unsigned(r.mcnt) = 0 then
n.msec := '1';
n.mcnt := conv_std_logic_vector(MSECDIV-1,10);
n.mcnt := slv(to_unsigned(MSECDIV-1,10));
end if;
end if;

15
rtl/vlib/genlib/debounce_gen.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: debounce_gen.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: debounce_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,10 @@
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2007-12-26 105 1.0.2 add default for RESET
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-29 61 1.0 Initial version
@@ -28,7 +29,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -76,7 +77,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS.cecnt <= cntzero;
R_REGS.dref <= DI;
@@ -107,7 +108,7 @@ begin
if CE_INT = '1' then
if unsigned(r.cecnt) = 0 then
n.cecnt := conv_std_logic_vector(CEDIV-1,CWIDTH);
n.cecnt := slv(to_unsigned(CEDIV-1,CWIDTH));
n.dref := DI;
n.dchange := datazero;
for i in DI'range loop
@@ -117,7 +118,7 @@ begin
end loop;
else
n.cecnt := unsigned(r.cecnt) - 1;
n.cecnt := slv(unsigned(r.cecnt) - 1);
end if;
end if;

19
rtl/vlib/genlib/genlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: genlib.vhd 389 2011-07-07 21:59:00Z mueller $
-- $Id: genlib.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,6 +19,7 @@
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-09 421 1.0.8 add cdc_pulse
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
@@ -153,4 +154,18 @@ component timer is -- retriggerable timer
);
end component;
component cdc_pulse is -- clock domain cross for pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false); -- if true: busy waits for ack
port (
CLKM : in slbit; -- clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end component;
end package genlib;

3
rtl/vlib/memlib/fifo_1c_dram.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: fifo_1c_dram.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: fifo_1c_dram.vhd 421 2011-11-07 21:23:50Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -36,7 +36,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.memlib.all;

23
rtl/vlib/memlib/fifo_1c_dram_raw.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: fifo_1c_dram_raw.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: fifo_1c_dram_raw.vhd 421 2011-11-07 21:23:50Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,16 +20,17 @@
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-03 47 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
@@ -63,9 +64,9 @@ architecture syn of fifo_1c_dram_raw is
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
conv_std_logic_vector(0,AWIDTH),
conv_std_logic_vector(0,AWIDTH),
'1','0'
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
@@ -92,7 +93,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
@@ -116,7 +117,7 @@ begin
re_val := RE and not r.empty;
we_val := WE and ((not r.full) or RE);
isize := unsigned(r.waddr) - unsigned(r.raddr);
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
iram_we := '0';
if RESET = '1' then
@@ -125,7 +126,7 @@ begin
else
if we_val = '1' then
n.waddr := unsigned(r.waddr) + 1;
n.waddr := slv(unsigned(r.waddr) + 1);
iram_we := '1';
if re_val = '0' then
n.empty := '0';
@@ -136,7 +137,7 @@ begin
end if;
if re_val = '1' then
n.raddr := unsigned(r.raddr) + 1;
n.raddr := slv(unsigned(r.raddr) + 1);
if we_val = '0' then
n.full := '0';
if unsigned(isize) = 1 then

24
rtl/vlib/memlib/memlib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: memlib.vhd 389 2011-07-07 21:59:00Z mueller $
-- $Id: memlib.vhd 424 2011-11-13 16:38:23Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -17,7 +17,7 @@
-- asynchronus rams; Fifo's.
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
@@ -222,16 +222,16 @@ component fifo_2c_dram is -- fifo, 2 clock, dram based
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- reset (synchronous with CLKW)
RESETR : in slbit; -- reset (synchronous with CLKR)
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- number slots to write (synch w/ CLKW)
SIZER : out slv(AWIDTH-1 downto 0) -- number slots to read (synch w/ CLKR)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end component;

19
rtl/vlib/memlib/ram_1swar_1ar_gen.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ram_1swar_1ar_gen.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ram_1swar_1ar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -22,10 +22,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0.1 use std_logic_arith, not _unsigned; use unsigned()
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
@@ -42,7 +43,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -75,14 +76,14 @@ begin
proc_clk: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if WE = '1' then
RAM(conv_integer(unsigned(ADDRA))) <= DI;
RAM(to_integer(unsigned(ADDRA))) <= DI;
end if;
end if;
end process proc_clk;
DOA <= RAM(conv_integer(unsigned(ADDRA)));
DOB <= RAM(conv_integer(unsigned(ADDRB)));
DOA <= RAM(to_integer(unsigned(ADDRA)));
DOB <= RAM(to_integer(unsigned(ADDRB)));
end syn;

17
rtl/vlib/memlib/ram_1swar_gen.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ram_1swar_gen.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ram_1swar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -22,10 +22,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0.1 use std_logic_arith, not _unsigned; use unsigned()
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
@@ -38,7 +39,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -69,13 +70,13 @@ begin
proc_clk: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if WE = '1' then
RAM(conv_integer(unsigned(ADDR))) <= DI;
RAM(to_integer(unsigned(ADDR))) <= DI;
end if;
end if;
end process proc_clk;
DO <= RAM(conv_integer(unsigned(ADDR)));
DO <= RAM(to_integer(unsigned(ADDR)));
end syn;

17
rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ram_1swsr_wfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ram_1swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -27,18 +27,19 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned();
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -73,12 +74,12 @@ begin
proc_clk: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if EN = '1' then
if WE = '1' then
sv_ram(conv_integer(unsigned(ADDR))) := DI;
sv_ram(to_integer(unsigned(ADDR))) := DI;
end if;
R_DO <= sv_ram(conv_integer(unsigned(ADDR)));
R_DO <= sv_ram(to_integer(unsigned(ADDR)));
end if;
end if;
end process proc_clk;

23
rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ram_2swsr_rfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ram_2swsr_rfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -22,11 +22,12 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned();
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- now initialize DO to all '0' at start
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
@@ -34,7 +35,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -75,11 +76,11 @@ begin
proc_clka: process (CLKA)
begin
if CLKA'event and CLKA='1' then
if rising_edge(CLKA) then
if ENA = '1' then
R_DOA <= sv_ram(conv_integer(unsigned(ADDRA)));
R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
if WEA = '1' then
sv_ram(conv_integer(unsigned(ADDRA))) := DIA;
sv_ram(to_integer(unsigned(ADDRA))) := DIA;
end if;
end if;
end if;
@@ -87,11 +88,11 @@ begin
proc_clkb: process (CLKB)
begin
if CLKB'event and CLKB='1' then
if rising_edge(CLKB) then
if ENB = '1' then
R_DOB <= sv_ram(conv_integer(unsigned(ADDRB)));
R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
if WEB = '1' then
sv_ram(conv_integer(unsigned(ADDRB))) := DIB;
sv_ram(to_integer(unsigned(ADDRB))) := DIB;
end if;
end if;
end if;

23
rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ram_2swsr_wfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ram_2swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -22,18 +22,19 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned();
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -73,24 +74,24 @@ begin
proc_clka: process (CLKA)
begin
if CLKA'event and CLKA='1' then
if rising_edge(CLKA) then
if ENA = '1' then
if WEA = '1' then
sv_ram(conv_integer(unsigned(ADDRA))) := DIA;
sv_ram(to_integer(unsigned(ADDRA))) := DIA;
end if;
R_DOA <= sv_ram(conv_integer(unsigned(ADDRA)));
R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
end if;
end if;
end process proc_clka;
proc_clkb: process (CLKB)
begin
if CLKB'event and CLKB='1' then
if rising_edge(CLKB) then
if ENB = '1' then
if WEB = '1' then
sv_ram(conv_integer(unsigned(ADDRB))) := DIB;
sv_ram(to_integer(unsigned(ADDRB))) := DIB;
end if;
R_DOB <= sv_ram(conv_integer(unsigned(ADDRB)));
R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
end if;
end if;
end process proc_clkb;

11
rtl/vlib/rbus/rb_mon.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rb_mon.vhd 346 2010-12-22 22:59:26Z mueller $
-- $Id: rb_mon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -17,10 +17,11 @@
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
@@ -35,7 +36,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -99,7 +100,7 @@ begin
wait until ENA='1'; -- stall process till enabled
end if;
wait until CLK'event and CLK='1'; -- check at end of clock cycle
wait until rising_edge(CLK); -- check at end of clock cycle
if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
if RB_SRES.err = '1' then

17
rtl/vlib/rbus/rbd_bram.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rbd_bram.vhd 372 2011-03-20 22:48:11Z mueller $
-- $Id: rbd_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2010-12-31 352 1.0.2 simplify irb_ack logic
-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x
-- 2010-12-26 349 1.0 Initial version
@@ -44,7 +45,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
@@ -53,7 +54,7 @@ use work.rblib.all;
entity rbd_bram is -- rbus dev: rbus bram test target
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11110100#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#11110100#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -109,7 +110,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
@@ -165,7 +166,7 @@ begin
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := unsigned(r.cntbusy) - 1; -- decrement busy timer
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
end if;
@@ -186,7 +187,7 @@ begin
ibramwe := '1';
end if;
if irbena = '1' then
n.addr := unsigned(r.addr) + 1;
n.addr := slv(unsigned(r.addr) + 1);
end if;
end if;

19
rtl/vlib/rbus/rbd_eyemon.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: rbd_eyemon.vhd 406 2011-08-14 21:06:44Z mueller $
-- $Id: rbd_eyemon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -29,6 +29,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..)
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
@@ -56,7 +57,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
@@ -64,8 +65,8 @@ use work.rblib.all;
entity rbd_eyemon is -- rbus dev: eye monitor for serport's
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11111000#,8);
RDIV : slv8 := conv_std_logic_vector(0,8));
RB_ADDR : slv8 := slv(to_unsigned(2#11111000#,8));
RDIV : slv8 := slv(to_unsigned(0,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -160,7 +161,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
@@ -313,7 +314,7 @@ begin
laddr_inc := '1';
end if;
else
n.rdivcnt := unsigned(r.rdivcnt) - 1;
n.rdivcnt := slv(unsigned(r.rdivcnt) - 1);
end if;
when s_clr => -- s_clr: clear memory ---------------
@@ -333,7 +334,7 @@ begin
elsif laddr_clr = '1' then
n.laddr := (others=>'0');
elsif laddr_inc = '1' then
n.laddr := unsigned(r.laddr) + 1;
n.laddr := slv(unsigned(r.laddr) + 1);
end if;
n.laddr_1 := r.laddr;
@@ -341,7 +342,7 @@ begin
ibramdi := (others=>'0');
if r.memclr = '0' then
ibramdi := unsigned(BRAM_DOA) + 1;
ibramdi := slv(unsigned(BRAM_DOA) + 1);
end if;
N_REGS <= n;

19
rtl/vlib/rbus/rbd_rbmon.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: rbd_rbmon.vhd 387 2011-07-03 17:24:52Z mueller $
-- $Id: rbd_rbmon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
@@ -63,7 +64,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
@@ -71,7 +72,7 @@ use work.rblib.all;
entity rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11111100#,8);
RB_ADDR : slv8 := slv(to_unsigned(2#11111100#,8));
AWIDTH : positive := 9);
port (
CLK : in slbit; -- clock
@@ -197,7 +198,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
@@ -282,7 +283,7 @@ begin
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
n.waddr := unsigned(r.waddr) + 1;
n.waddr := slv(unsigned(r.waddr) + 1);
if r.waddr = "11" then
laddr_inc := '1';
end if;
@@ -352,7 +353,7 @@ begin
n.rberr := '1';
end if;
if r.rbnbusy /= rbnbusylast then -- and count
n.rbnbusy := unsigned(r.rbnbusy) + 1;
n.rbnbusy := slv(unsigned(r.rbnbusy) + 1);
end if;
end if;
n.rbnak := not RB_SRES_SUM.ack;
@@ -368,13 +369,13 @@ begin
n.rbndly := (others=>'0'); -- clear delay counter
else -- just idle
if r.rbndly /= rbndlylast then -- count cycles
n.rbndly := unsigned(r.rbndly) + 1;
n.rbndly := slv(unsigned(r.rbndly) + 1);
end if;
end if;
end if;
if laddr_inc = '1' then
n.laddr := unsigned(r.laddr) + 1;
n.laddr := slv(unsigned(r.laddr) + 1);
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
end if;

17
rtl/vlib/rbus/rbd_tester.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rbd_tester.vhd 369 2011-03-13 22:39:26Z mueller $
-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: rlink/tb/tb_rlink (used as test target)
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -29,6 +29,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.4 now numeric_std clean
-- 2010-12-31 352 1.0.3 simplify irb_ack logic
-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
@@ -51,7 +52,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
@@ -60,7 +61,7 @@ use work.rblib.all;
entity rbd_tester is -- rbus dev: rbus tester
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#11110000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -146,7 +147,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
@@ -208,10 +209,10 @@ begin
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := unsigned(r.cntbusy) - 1; -- decrement busy timer
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
if r.cntcyc /= cntcyc_max then -- if cycle counter < max
n.cntcyc := unsigned(r.cntcyc) + 1; -- increment cycle counter
n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
end if;
end if;

15
rtl/vlib/rbus/rbd_timer.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rbd_timer.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: rbd_timer.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
--
@@ -40,14 +41,14 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
entity rbd_timer is -- rbus dev: usec precision timer
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#00000000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#00000000#,8)));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
@@ -82,7 +83,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
@@ -132,7 +133,7 @@ begin
n.timer_act := '0'; -- mark unactive
n.timer_end := '1'; -- send end marker
else -- else: timer not at end
n.timer := unsigned(r.timer) - 1; -- decrement
n.timer := slv(unsigned(r.timer) - 1); -- decrement
end if;
end if;
end if;

30
rtl/vlib/rbus/rbdlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rbdlib.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: rbdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,10 +16,11 @@
-- Description: Definitions for rbus devices
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2010-12-29 351 1.2 new address layout; add rbd_timer
-- 2010-12-27 349 1.1 now correct defs for _rbmon and _eyemon
-- 2010-12-04 343 1.0 Initial version
@@ -37,17 +38,26 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package rbdlib is
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.
constant rbaddr_tester : slv8 := slv(to_unsigned(2#11110000#,8));
constant rbaddr_bram : slv8 := slv(to_unsigned(2#11110100#,8));
constant rbaddr_rbmon : slv8 := slv(to_unsigned(2#11111100#,8));
constant rbaddr_eyemon : slv8 := slv(to_unsigned(2#11111000#,8));
constant rbaddr_timer : slv8 := slv(to_unsigned(2#00000000#,8));
component rbd_tester is -- rbus dev: rbus tester
-- complete rbus_aif interface
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8));
RB_ADDR : slv8 := rbaddr_tester);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -61,7 +71,7 @@ end component;
component rbd_bram is -- rbus dev: bram test target
-- incomplete rbus_aif interface
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11110100#,8));
RB_ADDR : slv8 := rbaddr_bram);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -72,7 +82,7 @@ end component;
component rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11111100#,8);
RB_ADDR : slv8 := rbaddr_rbmon;
AWIDTH : positive := 9);
port (
CLK : in slbit; -- clock
@@ -85,8 +95,8 @@ end component;
component rbd_eyemon is -- rbus dev: eye monitor for serport's
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11111000#,8);
RDIV : slv8 := conv_std_logic_vector(0,8));
RB_ADDR : slv8 := rbaddr_eyemon;
RDIV : slv8 := (others=>'0'));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -99,7 +109,7 @@ end component;
component rbd_timer is -- rbus dev: usec precision timer
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#00000000#,8));
RB_ADDR : slv8 := rbaddr_timer);
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse

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