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https://github.com/wfjm/w11.git
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e91847f8db
- added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated
86 lines
3.1 KiB
Plaintext
86 lines
3.1 KiB
Plaintext
FLOWTYPE = FPGA_SYNTHESIS;
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#
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# $Id: syn_s6_speed.opt 537 2013-10-06 09:06:23Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2013-10-05 537 1.2 define all, use -opt_level=2, -shreg_min_size=3
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# 2012-02-05 456 1.1 use $top_entity variable for -top attribute
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# 2011-08-13 405 1.0 Initial version
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#
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# Derived from ISE xst_mixed.opt
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#
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# ----------------------------------------------------------------------------
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# Options for XST
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#
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Program xst
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-ifn <design>_xst.scr; # input XST script file
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-ofn <design>_xst.log; # output XST log file
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-intstyle xflow; # Message Reporting Style
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#
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# ParamFile lists the XST Properties that can be set by the user.
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#
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ParamFile: <design>_xst.scr
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"run";
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#
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# Global Synthesis Options
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#
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"-ifn <synthdesign>"; # Input/Project File Name
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"-ifmt mixed"; # Input Format (Verilog and VHDL)
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"-ofn <design>"; # Output File Name
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"-ofmt ngc"; # Output File Format
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"-top $top_entity"; # Top Design Name
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"-p <partname>"; # Target Device
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"-uc <design>.xcf"; # Constraint File name
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"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
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"-opt_level 2"; # Optimization Effort Criteria def=1 !
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"-power NO"; # def
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"-iuc NO"; # def
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"-keep_hierarchy No"; # def
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"-netlist_hierarchy As_Optimized";# def
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"-rtlview No"; # def=yes if from ISE
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"-glob_opt AllClockNets"; # likely def
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"-read_cores YES"; # def (irrelevant)
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"-write_timing_constraints NO"; # def
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"-cross_clock_analysis NO"; # def
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"-hierarchy_separator /"; # ?
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"-bus_delimiter <>"; # def
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"-case Maintain"; # def
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"-slice_utilization_ratio 100"; # ?
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"-bram_utilization_ratio 100"; # ?
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"-dsp_utilization_ratio 100"; # ?
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"-lc Auto"; # def
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"-reduce_control_sets Auto"; # def
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"-fsm_extract YES"; # def
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"-fsm_encoding Auto"; # def
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"-safe_implementation No"; # def
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"-fsm_style LUT"; # def
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"-ram_extract Yes"; # def
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"-ram_style Auto"; # def
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"-rom_extract Yes"; # def
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"-rom_style Auto"; # def
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"-shreg_extract YES"; # def
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"-shreg_min_size 3"; # default is 2 !!
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"-auto_bram_packing NO"; # def
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"-resource_sharing YES"; # def
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"-async_to_sync NO"; # def
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"-use_dsp48 Auto"; # def
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"-iobuf YES"; # def
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"-max_fanout 100000"; # def
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"-bufg 16"; # def (for S-6)
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"-register_duplication YES"; # def
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"-register_balancing No"; # def
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"-optimize_primitives NO"; # def
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"-use_clock_enable Auto"; # def
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"-use_sync_set Auto"; # def
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"-use_sync_reset Auto"; # def
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"-iob Auto"; # ?
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"-equivalent_register_removal YES"; # def
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"-slice_utilization_ratio_maxmargin 5"; # ?
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#
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# The following are HDL Options
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#
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End ParamFile
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End Program xst
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#
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