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Code Issues Releases Wiki Activity

- added support for Vivado

Browse Source 
- added support for Nexys4 and Basys3 boards
- added RL11 disk support
- lots of documentation updated
This commit is contained in:
Walter F.J. Mueller
2015-03-09 19:26:25 +00:00
parent dde49d52e4
commit e91847f8db
588 changed files with 13843 additions and 4540 deletions
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224
Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 623 2014-12-29 19:11:40Z mueller $
# $Id: Makefile 650 2015-02-22 21:39:47Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -6,6 +6,8 @@
#
# Revision History:
# Date Rev Version Comment
# 2015-02-01 640 1.2 add vivado targets, separate from ise targets
# 2015-01-25 638 1.1 drop as type fx2 targets
# 2014-06-14 562 1.0.8 suspend nexys4 syn targets
# 2013-09-28 535 1.0.7 add nexys4 port for sys_gen/tst_sram,w11a
# 2013-05-01 513 1.0.6 add clean_sim_tmp and clean_syn_tmp targets
@@ -16,98 +18,185 @@
# 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio
# 2011-07-09 391 1.0 Initial version
#
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic3
SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic
SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic3
SYN_all += rtl/sys_gen/tst_rlink/nexys2
SYN_all += rtl/sys_gen/tst_rlink/nexys3
SYN_all += rtl/sys_gen/tst_rlink/s3board
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
SYN_all += rtl/sys_gen/tst_rlink_cuff/atlys/ic
SYN_all += rtl/sys_gen/tst_serloop/nexys2
SYN_all += rtl/sys_gen/tst_serloop/nexys3
SYN_all += rtl/sys_gen/tst_serloop/s3board
SYN_all += rtl/sys_gen/tst_snhumanio/atlys
SYN_all += rtl/sys_gen/tst_snhumanio/nexys2
SYN_all += rtl/sys_gen/tst_snhumanio/nexys3
SYN_all += rtl/sys_gen/tst_snhumanio/s3board
SYN_all += rtl/sys_gen/w11a/nexys2
SYN_all += rtl/sys_gen/w11a/nexys3
SYN_all += rtl/sys_gen/w11a/s3board
SIM_all += rtl/bplib/nxcramlib/tb
SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_all += rtl/sys_gen/tst_serloop/s3board/tb
SIM_all += rtl/sys_gen/w11a/nexys2/tb
SIM_all += rtl/sys_gen/w11a/nexys3/tb
SIM_all += rtl/sys_gen/w11a/s3board/tb
SIM_all += rtl/vlib/comlib/tb
SIM_all += rtl/vlib/rlink/tb
SIM_all += rtl/vlib/serport/tb
SIM_all += rtl/w11a/tb
# Synthesis targets --------------------------------------------------
# ISE based targets, by board type -----------------------
# S3board ------------------------------------
SYN_ise += rtl/sys_gen/tst_rlink/s3board
SYN_ise += rtl/sys_gen/tst_serloop/s3board
SYN_ise += rtl/sys_gen/tst_snhumanio/s3board
SYN_ise += rtl/sys_gen/w11a/s3board
# Nexys2 -------------------------------------
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_rlink/nexys2
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_serloop/nexys2
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2
SYN_ise += rtl/sys_gen/w11a/nexys2
# Nexys3 -------------------------------------
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3
SYN_ise += rtl/sys_gen/tst_rlink/nexys3
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
SYN_ise += rtl/sys_gen/tst_serloop/nexys3
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3
SYN_ise += rtl/sys_gen/w11a/nexys3
# xc2 ----------------------------------------
# Vivado based targets, by board type --------------------
# Basys3 -------------------------------------
SYN_viv += rtl/sys_gen/tst_snhumanio/basys3
#SYN_viv += rtl/sys_gen/tst_serloop/basys3
SYN_viv += rtl/sys_gen/tst_rlink/basys3
SYN_viv += rtl/sys_gen/w11a/basys3
# Nexys4 -------------------------------------
SYN_viv += rtl/sys_gen/tst_rlink/nexys4
SYN_viv += rtl/sys_gen/tst_serloop/nexys4
SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4
SYN_viv += rtl/sys_gen/w11a/nexys4
# Simulation targets -------------------------------------------------
# ISE flow -----------------------------------------------
# Component tests ----------------------------
SIM_ise += rtl/bplib/nxcramlib/tb
SIM_ise += rtl/vlib/comlib/tb
SIM_ise += rtl/vlib/rlink/tb
SIM_ise += rtl/vlib/serport/tb
SIM_ise += rtl/w11a/tb
# S3board ------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/s3board/tb
SIM_ise += rtl/sys_gen/tst_serloop/s3board/tb
SIM_ise += rtl/sys_gen/w11a/s3board/tb
# Nexys2 -------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/nexys2/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys2/tb
SIM_ise += rtl/sys_gen/w11a/nexys2/tb
# Nexys3 -------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/nexys3/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_ise += rtl/sys_gen/w11a/nexys3/tb
# xc2 ----------------------------------------
# Vivado flow --------------------------------------------
# Basys3 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb
#SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb
SIM_viv += rtl/sys_gen/w11a/basys3/tb
# Nexys4 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb
SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb
SIM_viv += rtl/sys_gen/w11a/nexys4/tb
#
.PHONY : default all all_sim all_syn
.PHONY : clean clean_sim clean_sim_tmp clean_sym clean_sym_tmp
.PHONY : $(SYN_all) $(SIM_all)
.PHONY : default
.PHONY : all all_ise all_viv
.PHONY : all_sim_ise all_syn_ise all_syn_viv
.PHONY : clean
.PHONY : clean_sim_ise clean_sim_ise_tmp
.PHONY : clean_sym_ise clean_sim_viv clean_sym_ise_tmp clean_sym_viv_tmp
#
# all directories most be declared as phony targets
.PHONY : $(SYN_ise) $(SIM_ise)
.PHONY : $(SYN_viv) $(SIM_viv)
#
default :
@echo "No default action defined:"
@echo " for VHDL simulation/synthesis use:"
@echo " make -j `nproc` all_sim"
@echo " make -j `nproc` all_syn"
@echo " make -j `nproc` all"
@echo " make -j `nproc` all_ise"
@echo " make -j `nproc` all_viv"
@echo " make -j `nproc` all_sim_ise"
@echo " make -j `nproc` all_syn_ise"
@echo " make -j `nproc` all_sim_viv"
@echo " make -j `nproc` all_syn_viv"
@echo " make clean"
@echo " make clean_sim"
@echo " make clean_syn"
@echo " make clean_sim_tmp"
@echo " make clean_syn_tmp"
@echo " make clean_sim_ise"
@echo " make clean_syn_ise"
@echo " make clean_sim_viv"
@echo " make clean_syn_viv"
@echo " make clean_sim_ise_tmp"
@echo " make clean_syn_ise_tmp"
@echo " make clean_sim_viv_tmp"
@echo " make clean_syn_viv_tmp"
@echo " for tool/documentation generation use:"
@echo " make -j `nproc` all_lib"
@echo " make clean_lib"
@echo " make all_tcl"
@echo " make all_dox"
#
all :
make -j `nproc` all_sim
make -j `nproc` all_syn
make -j `nproc` all_lib
all : all_ise all_viv all_lib
all_ise : all_sim_ise all_syn_ise
all_viv : all_sim_viv all_syn_viv
#
clean : clean_sim clean_syn
clean : clean_sim_ise clean_syn_ise clean_sim_viv clean_syn_viv
#
clean_sim :
for dir in $(SIM_all); do $(MAKE) -C $$dir clean; done
clean_syn :
for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done
clean_sim_ise :
for dir in $(SIM_ise); do $(MAKE) -C $$dir clean; done
clean_syn_ise :
for dir in $(SYN_ise); do $(MAKE) -C $$dir clean; done
#
clean_sim_tmp :
for dir in $(SIM_all); do $(MAKE) -C $$dir ghdl_tmp_clean; done
clean_syn_tmp :
for dir in $(SYN_all); do $(MAKE) -C $$dir ise_tmp_clean; done
clean_sim_viv :
for dir in $(SIM_viv); do $(MAKE) -C $$dir clean; done
clean_syn_viv :
for dir in $(SYN_viv); do $(MAKE) -C $$dir clean; done
#
all_sim : $(SIM_all)
clean_sim_ise_tmp :
for dir in $(SIM_ise); do $(MAKE) -C $$dir ghdl_tmp_clean; done
clean_syn_ise_tmp :
for dir in $(SYN_ise); do $(MAKE) -C $$dir ise_tmp_clean; done
#
all_syn : $(SYN_all)
clean_sim_viv_tmp :
for dir in $(SIM_viv); do $(MAKE) -C $$dir ghdl_tmp_clean; done
clean_syn_viv_tmp :
for dir in $(SYN_viv); do $(MAKE) -C $$dir viv_tmp_clean; done
#
all_sim_ise : $(SIM_ise)
#
all_syn_ise : $(SYN_ise)
@if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \
echo "++++++++++ some designs have no timing closure: ++++++++++"; \
find -name "*_par.log" | xargs grep -L 'All constraints were met'; \
echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
else \
echo "++++++++++ all ISE designs have timing closure ++++++++++"; \
fi
#
# Neither ghdl nor xst allow multiple parallel compiles in one directory.
# The following ensures that the sub-makes are called with -j 1 and will
# not try to run multiple compiles on one directory.
all_sim_viv : $(SIM_viv)
#
$(SIM_all):
all_syn_viv : $(SYN_viv)
@if [ -n "`find -name "*_rou_tim.rpt" | xargs grep -L 'All user specified timing constraints are met'`" ] ; then \
echo "++++++++++ some designs have no timing closure: ++++++++++"; \
find -name "*_rou_tim.rpt" | xargs grep -L 'All user specified timing constraints are met'; \
echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
else \
echo "++++++++++ all Vivado designs have timing closure ++++++++++"; \
fi
#
# Neither ghdl nor Xilinx tools allow multiple parallel compiles in one
# directory. The following ensures that the sub-makes are called with -j 1
# and will not try to run multiple compiles on one directory.
#
$(SIM_ise):
$(MAKE) -j 1 -C $@
$(SYN_all):
$(SYN_ise):
$(MAKE) -j 1 -C $@
#
$(SIM_viv):
$(MAKE) -j 1 -C $@
$(SYN_viv):
$(MAKE) -j 1 -C $@
#
all_lib :
@@ -122,3 +211,4 @@ all_dox :
(cd tools/dox; make_doxy)
#
all_all : all_sim all_syn all_lib all_tcl

2
doc/.cvsignore Normal file
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@@ -0,0 +1,2 @@
*_flow.dot
*_flow.pdf

21
doc/FILES.txt
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@@ -1,4 +1,4 @@
$Id: FILES.txt 577 2014-08-03 20:49:42Z mueller $
$Id: FILES.txt 645 2015-02-13 21:44:03Z mueller $
Short description of the directory layout, what is where ?
@@ -7,27 +7,33 @@ Short description of the directory layout, what is where ?
rtl VHDL sources
rtl/bplib - board and component support libs
rtl/bplib/atlys - for Digilent Atlys board
rtl/bplib/basys3 - for Digilent Basys3 board
rtl/bplib/fx2lib - for Cypress FX2 USB interface controller
rtl/bplib/issi - for ISSI parts
rtl/bplib/micron - for Micron parts
rtl/bplib/nexys2 - for Digilent Nexsy2 board
rtl/bplib/nexys3 - for Digilent Nexsy3 board
rtl/bplib/nexys4 - for Digilent Nexsy4 board
rtl/bplib/nxcramlib - for CRAM part used in Nexys2/3
rtl/bplib/s3board - for Digilent S3BOARD
rtl/bplib/s3board - for Digilent S3board
rtl/ibus - ibus devices (UNIBUS peripherals)
rtl/sys_gen - top level designs
rtl/sys_gen/tst_fx2loop - top level designs for Cypress FX2 tester
nexys2,nexys3 - systems for Nexsy2,Nexsy3
rtl/sys_gen/tst_rlink - top level designs for an rlink tester
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3board
basys3,nexys4 - systems for Basys3,Nexys4
rtl/sys_gen/tst_rlink_cuff - top level designs for rlink over FX2 tester
nexys2,nexys3,atlys - systems for Atlys,Nexsy2,Nexsy3
rtl/sys_gen/tst_serloop - top level designs for serport loop tester
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3board
nexys4 - systems for Nexys4
rtl/sys_gen/tst_snhumanio - top level designs for human I/O tester
atlys,nexys2,nexys3,s3board - systems for Atlys,Nexsy2,Nexsy3,S3BOARD
atlys,nexys2,nexys3,s3board - systems for Atlys,Nexsy2,Nexsy3,S3board
basys3,nexys4 - systems for Basys3,Nexys4
rtl/sys_gen/w11a - top level designs for w11a SoC
nexys2,nexys3,s3board - w11a systems for Nexsy2,Nexsy3,S3BOARD
nexys2,nexys3,s3board - w11a systems for Nexsy2,Nexsy3,S3board
basys3,nexys4 - systems for Basys3,Nexys4
rtl/vlib - VHDL component libs
rtl/vlib/comlib - communication
rtl/vlib/genlib - general
@@ -44,7 +50,8 @@ Short description of the directory layout, what is where ?
tools/asm-11/tests-err - test bench for asm-11 (error check part)
tools/bin - scripts and binaries
tools/dox - Doxygen documentation configuration
tools/make - make includes
tools/make_ise - make includes for ISE
tools/make_viv - make includes for Vivado
tools/fx2 - Firmware for Cypress FX2 USB Interface
tools/fx2/bin - pre-build firmware images in .ihx format
tools/fx2/src - C and asm sources

364
doc/INSTALL.txt
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@@ -1,4 +1,4 @@
# $Id: INSTALL.txt 604 2014-11-16 22:33:09Z mueller $
# $Id: INSTALL.txt 654 2015-03-01 18:45:38Z mueller $
Guide to install and build w11a systems, test benches and support software
@@ -6,23 +6,14 @@ Guide to install and build w11a systems, test benches and support software
1. Download
2. System requirements
3. Setup system environment
a. Setup environment variables
b. Setup USB access
3. Setup environment variables
4. Compile UNISIM/SIMPRIM libraries for ghdl
5. Compile and install the support software
a. Compile sharable libraries
b. Setup Tcl packages
c. Rebuild Cypress FX2 firmware
6. The build system
6 a. Setting up Xilinx environment with xtwi
7. Building test benches
a. General instructions
b. Available test benches
8. Building systems
a. General instructions
b. Configuring FPGAs (via make flow)
c. Configuring FPGAs (directly via config_wrapper)
d. Available systems
e. Available bitkits with bit and log files
9. Generate Doxygen based source code view
@@ -56,7 +47,6 @@ Guide to install and build w11a systems, test benches and support software
cd <wdir>
svn co -r <rev> http://opencores.org/ocsvn/w11/w11/trunk
2. System requirements ----------------------------------------------------
This project contains not only VHDL code but also support software. Therefore
@@ -64,7 +54,7 @@ Guide to install and build w11a systems, test benches and support software
list gives the Ubuntu/Debian package names, but mapping this to other
distributions should be straight forward.
- building the bit files for the FPGAs requires a Xilinx WebPACK installation
- building the bit files requires a Xilinx ISE WebPACK installation
- building and using the RLink backend software requires:
- full C/C++ development chain (gcc,g++,cpp,make)
@@ -75,25 +65,16 @@ Guide to install and build w11a systems, test benches and support software
- libusb 1.0 (>= 1.0.6)
-> package: libusb-1.0-0-dev
- Perl (>= 5.10) (usually included in base installations)
- Tcl (>= 8.4), with tclreadline support
- Tcl (>= 8.5), with tclreadline support
-> package: tcl tcl-dev tcllib tclreadline
- the download contains pre-build firmware images for the Cypress FX2
USB Interface. Re-building them requires
- Small Device C Compiler
-> package: sdcc sdcc-ucsim
- for FX2 firmware download and jtag programming over USB one needs
- fxload
-> package: fxload
- urjtag
-> package: urjtag for Ubuntu 12.04
-> see INSTALL_urjtag.txt for other distributions !!
- for VHDL simulations one needs
- ghdl
-> see INSTALL_ghdl.txt for the unfortunately gory details
- additional requirements for using Cypress FX (on Nexys2/3) see
INSTALL_fx2_support.txt
- for doxygen documentation an up-to-date installation of doxygen is
required, version 1.8.3.1 or later
@@ -101,13 +82,11 @@ Guide to install and build w11a systems, test benches and support software
- gtkwave
-> package: gtkwave
3. Setup system environment -----------------------------------------------
3a. Setup environment variables --------------------------------------
3. Setup environment variables --------------------------------------------
The make flow for building test benches (ghdl and ISim based) and systems
(Xilinx xst based) as well as the support software (mainly the rlink backend
server) requires
(Xilinx ISE xst based) as well as the support software (mainly the rlink
backend server) requires
- the definition of the environment variables:
- RETROBASE: must refer to the installation root directory
@@ -143,32 +122,7 @@ Guide to install and build w11a systems, test benches and support software
After that building functional model based test benches will work. If you
want to also build post-xst or post-par test benches read next section.
If the Cypress USB controller available on Digilent Nexys2, Nexys3 and
Atlys boards is used the default USB VID and PID is defined by two
environment variables. For internal lab use one can use
export RETRO_FX2_VID=16c0
export RETRO_FX2_PID=03ef
!! Carefully read the disclaimer about usage of USB VID/PID numbers !!
!! in the file README_USB-VID-PID.txt. You'll be responsible for any !!
!! misuse of the defaults provided with the project sources. !!
!! Usage of this VID/PID in any commercial product is forbidden. !!
3b. Setup USB access -------------------------------------------------
For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
Atlys boards 'udev' rules must be setup to allow user level access to
these devices. A set of rules is provided under
$RETROBASE/tools/fx2/sys
Follow the 'README.txt' file in this directory.
Notes:
- the provided udev rules use the VID/PID for 'internal lab use' as
described above. If other VID/PID used the file must be modified.
- your user account must be in group 'plugdev' (should be the default).
For Cypress FX2 (on Nexys2/3) related setup see INSTALL_fx2_support.txt
4. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
@@ -176,7 +130,7 @@ Guide to install and build w11a systems, test benches and support software
the gate level models derived after the xst, map or par step. In this
case ghdl has to link against a compiled UNISIM or SIMPRIM library.
To make handling of the parallel installion of several WebPack versions
To make handling of the parallel installion of several ISE WebPack versions
easy the compiled libraries are stored in sub-directories under $XILINX:
$XILINX/ghdl/unisim
@@ -187,8 +141,8 @@ Guide to install and build w11a systems, test benches and support software
<setup XTWI_PATH, see section 6a.>
cd $RETROBASE
xtwi xilinx_ghdl_unisim
xtwi xilinx_ghdl_simprim
xise_ghdl_unisim
xise_ghdl_simprim
If you have several WebPack versions installed, repeat for each version.
@@ -196,14 +150,20 @@ Guide to install and build w11a systems, test benches and support software
5a. Compile sharable libraries ---------------------------------------
Note: some c++11 features are used in the code
- N2343: decltype (used by boost bind) -> since gcc 4.3
- N2431: nullptr -> since gcc 4.6
- N2930: range based for -> since gcc 4.6
- N1984: auto-types variables -> since gcc 4.4
Required tools and libraries:
g++ >= 4.3 (decltype support assumed in usage of boost::bind)
g++ >= 4.6 (see c++11 usage above)
boost >= 1.35 (boost::thread api changed, new one is used)
linusb >= 1.0.5 (timerfd support)
Build was tested under:
ubuntu lucid (12.04 LTS): gcc 4.6.3 boost 1.46.1 libusb 1.0.9
debian squezze (6.0.6): gcc 4.4.5 boost 1.46.1 libusb 1.0.8
ubuntu precise (14.04 LTS): gcc 4.8.2 boost 1.54 libusb 1.0.17
debian wheezy (7.0.8): gcc 4.7.2 boost 1.49 libusb 1.0.11
To build all sharable libraries
@@ -248,228 +208,60 @@ Guide to install and build w11a systems, test benches and support software
ln -s $RETROBASE/tools/tcl/.tclshrc .
ln -s $RETROBASE/tools/tcl/.wishrc .
5c. Rebuild Cypress FX2 firmware -------------------------------------
The download includes pre-build firmware images for the Cypress FX2
USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.
These firmware images are under
$RETROBASE/tools/fx2/bin
To re-build them, e.g. because a different USB VID/PID is to be used
cd $RETROBASE/tools/fx2/src
make clean
make
make install
Note: The default build assumes that sdcc with a version 3.x is installed.
In case sdcc 2.x is installed use
make SDCC29=1
instead. See also tools/fx2/src/README.txt in the
Please read README_USB_VID-PID.txt carefully to understand the usage
of USB VID and PID.
6. The build system -------------------------------------------------------
Simulation and synthesis tools usually need a list of the VHDL source
files, often in proper compilation order (libraries before components).
The different tools have different formats of these 'project files'.
The build system employed in this project is based on manifest files called
'vbom' or "VHDL bill of material" files
which list for each vhdl source file the libraries and sources for the
instantiated components, the later via their vbom, and last but not least
the name of the vhdl source file.
All file name are relative to the current directory. A recursive traversal
through all vbom's gives for each vhld module all sources needed to compile
it. The vbomconv script in tools/bin does this, and generates depending on
options
- make dependency files
- ISE xst project files
- ISE ISim project files
- ghdl commands for analysis, inspection and make step
The master make files contain pattern rules like
%.ngc : %.vbom -- synthesize with xst
% : %.vbom -- build functional model test bench
which encapsulate all the vbomconf magic
A full w11a is build from about 100 source files, test benches from
even more. Using the vbom's a large number of designs can be easily
maintained.
6a. Setting up Xilinx environment with xtwi --------------------------
The Xilinx ISE setup script redefines PATH and LD_LIBRARY_PATH. The ISE
tools run fine in this environment, but other installed programs on the
system can (and actually do) fail.
The build system uses a small wrapper script called xtwi to encapsulate
the Xilinx environment. It expects that the environment variable XTWI_PATH
is setup to the install path of the ISE version to be used. Without the
/ISE_DS/ which is added by the ISE installation procedure !
Note: don't run the ISE setup scripts ..../settings(32|64).sh in your
working shell. Setup only XTWI_PATH !
The generation of
- FPGA firmware (e.g. .bit files)
- test benches (e.g. simulator images)
is based on make flows.
Two design tools are currently supported
- Xilinx Vivado
- Artix-7 based board (Basys3, Nexys4)
- see README_buildsystem_Vivado.txt
- Xilinx ISE
- Spartan-3 and Spartan-6 based boards (S3board, Nexys2, Nexys3)
- see README_buildsystem_ISE.txt
7. Building test benches --------------------------------------------------
7a. General instructions ---------------------------------------------
General instructions are in
- README_buildsystem_Vivado.txt (for Basys3, Nexys4)
- README_buildsystem_ISE.txt (for S3board, Nexys2, Nexys3)
To compile a test bench named <tbench> all is needed is
For available test benches see w11a_tb_guide.txt
make <tbench>
8. Building systems and configuring FPGAs ---------------------------------
The make file will use <tbench>.vbom, create all make dependency files,
and generate the needed ghdl commands.
In many cases the test benches can also be compiled against the gate
level models derived after the xst, map or par step. To compile them
make ghdl_tmp_clean
make <tbench>_ssim # for post-xst
make <tbench>_fsim # for post-map
make <tbench>_tsim # for post-par
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
7b. Available test benches -------------------------------------------
See file w11a_tb_guide.txt
8. Building systems -------------------------------------------------------
8a. General instructions ---------------------------------------------
First ensure that XTWI_PATH is setup, see section 6a.
To generate a bit file for a system named <sys> all is needed is
make <sys>.bit
The make file will use <sys>.vbom, create all make dependency files, build
the ucf file with cpp, and run the synthesis flow (xst, ngdbuild, par, trce).
The log files will be named
<sys>_xst.log # xst log file
<sys>_tra.log # translate (ngdbuild) log file (renamed %.bld)
<sys>_map.log # map log file (renamed %_map.mrp)
<sys>_par.log # par log file (renamed %.par)
<sys>_pad.log # pad file (renamed %_pad.txt)
<sys>_twr.log # trce log file (renamed %.twr)
To load the bitfile with WebPack impact into the target board use
make <sys>.iconfig
For boards with a Cypress FX2 USB controller load the bitfile directly with
make <sys>.jconfig
If a svf file is required for configuring the FPGA a svf can be created
from a bit file with
make <sys>.svf
If only the xst or par output is wanted just use
make <sys>.ngc
make <sys>.ncd
A simple 'message filter' system is also integrated into the make build flow.
For many (though not all) systems a .mfset file has been provided which
defines the xst,par and bitgen messages which are considered ok. To see
only the remaining message extracted from the vaious .log files simply
use the make target
make <sys>.mfsum
after a re-build.
8b. Configuring FPGAs (via make flow) --------------------------------
The make flow supports also loading the bitstream into FPGAs, either
via Xilinx Impact, or via the Cypress FX2 USB controller is available.
For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
simply use
make <sys>.iconfig
For using the Cypress FX2 USB controller on Digilent Nexys2, Nexys3 and
Atlys boards just connect the USB cable and
make <sys>.jconfig
This will automatically check and optionaly re-load the FX2 firmware
to a version matching the FPGA design, generate a .svf file from the
.bit file, and configure the FPGA. In case the bit file is out-of-date
the whole design will be re-implemented before.
8c. Configuring FPGAs (directly via config_wrapper) ------------------
The make flow described above uses two scripts
config_wrapper # must be used with xtwi !
fx2load_wrapper
which can be used directly for loading available bit or svf files into
the FPGA. For detailed documentation see the respective man pages.
Examples for the supported boards are given in section 8e.
General instructions are in
- README_buildsystem_Vivado.txt (for Basys3, Nexys4)
- README_buildsystem_ISE.txt (for S3board, Nexys2, Nexys3)
8d. Available systems ------------------------------------------------
Currently ready to build versions exist for
- Digilent S3BOARD (-1000 FPGA version)
- Digilent Nexys2 board (-1200 FPGA version)
- Digilent Nexys3 board
Ready to build designs are organized in the directories
$RETROBASE/rtl/sys_gen/<design>/<board>
with <design>
w11a w11a system
tst_rlink rlink over serial link tester
tst_rlink_cuff rlink over FX2 interface tester
and <board>
basys3 b3: Digilent Basys3 board
nexys4 n4: Digilent Nexys4 board (cellular RAM version)
nexys3 n3: Digilent Nexys3 board
nexys2 n2: Digilent Nexys2 board (-1200 FPGA version)
s3board s3: Digilent S3board (-1000 FPGA version)
To build the designs locally use
1. rlink tester
a. for Digilent S3BOARD
cd $RETROBASE/rtl/sys_gen/<design>/<board>
make sys_<dtype>_<btype>.bit
cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board
make sys_tst_rlink_s3.bit
b. for Digilent Nexys2 board
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2
make sys_tst_rlink_n2.bit
c. for Digilent Nexys3 board
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3
make sys_tst_rlink_n3.bit
2. rlink over USB tester
a. for Digilent Nexys2 board
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic
make sys_tst_rlink_cuff_ic_n2.bit
b. for Digilent Nexys3 board
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic
make sys_tst_rlink_cuff_ic_n3.bit
3. w11a systems
a. for Digilent S3BOARD
cd $RETROBASE/rtl/sys_gen/w11a/s3board
make sys_w11a_s3.bit
b. for Digilent Nexys2 board
cd $RETROBASE/rtl/sys_gen/w11a/nexys2
make sys_w11a_n2.bit
c. for Digilent Nexys3 board
cd $RETROBASE/rtl/sys_gen/w11a/nexys3
make sys_w11a_n3.bit
with in most cases <dtype> = <design> and <code> = 2 letter abriviation for
the board, e.g. n4 for nexys4.
8e. Available bitkits with bit and log files -------------------------
@@ -480,29 +272,35 @@ Guide to install and build w11a systems, test benches and support software
file names contain information about release, Xlinix tool, and design:
<release>_<tool>_<design>.tgz
These designs can be loaded with config_wrapper into the FPGA. The
procedures for the supported boards are given below.
- Vivado based designs:
These designs can be loaded with the Vivado hardware server into the FPGA.
Notes:
1. XTWI_PATH and RETROBASE environment variables must be defined.
2. config_wrapper bit2svf is only needed once to create the svf files.
3. fx2load_wrapper is needed once after each board power on.
- ISE based designs:
a. for Digilent S3BOARD (using ISE Impact)
These designs can be loaded with config_wrapper into the FPGA. The
procedures for the supported boards are given below.
xtwi config_wrapper --board=s3board iconfig <design>.bit
Notes:
1. XTWI_PATH and RETROBASE environment variables must be defined.
2. config_wrapper bit2svf is only needed once to create the svf files.
3. fx2load_wrapper is needed once after each board power on.
b. for Digilent Nexys2 board (using Cypress FX2 USB controller)
a. for Digilent Nexys3 board (using Cypress FX2 USB controller)
xtwi config_wrapper --board=nexys3 bit2svf <design>.bit
fx2load_wrapper --board=nexys3
xtwi config_wrapper --board=nexys3 jconfig <design>.svf
b. for Digilent Nexys2 board (using Cypress FX2 USB controller)
xtwi config_wrapper --board=nexys2 bit2svf <design>.bit
fx2load_wrapper --board=nexys2
xtwi config_wrapper --board=nexys2 jconfig <design>.svf
c. for Digilent Nexys3 board (using Cypress FX2 USB controller)
c. for Digilent S3board (using ISE Impact)
xtwi config_wrapper --board=s3board iconfig <design>.bit
xtwi config_wrapper --board=nexys3 bit2svf <design>.bit
fx2load_wrapper --board=nexys3
xtwi config_wrapper --board=nexys3 jconfig <design>.svf
9. Generate Doxygen based source code view --------------------------------

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@@ -0,0 +1,79 @@
# $Id: INSTALL_fx2_support.txt 654 2015-03-01 18:45:38Z mueller $
The Nexys2 and Nexys3 board feature a Cypress FX2 USB interface. It allows
to configure the FPGA and to transfer between FPGA and a PC. The retro
project uses a custom firmware in the FX2, this writeup describes the
installation of tools, environment setup and generation of the FX2 firmware.
Table of content:
1. System requirements
2. Setup environment variables
3. Setup USB access
4. Rebuild Cypress FX2 firmware
1. System requirements ----------------------------------------------------
- the download contains pre-build firmware images for the Cypress FX2
USB Interface. Re-building them requires
- Small Device C Compiler
-> package: sdcc sdcc-ucsim
- for FX2 firmware download and jtag programming over USB one needs
- fxload
-> package: fxload
- urjtag
-> package: urjtag for Ubuntu 12.04
-> see INSTALL_urjtag.txt for other distributions !!
2. Setup environment variables ---------------------------------------------
The default USB VID and PID is defined by two environment variables.
For internal lab use one can use
export RETRO_FX2_VID=16c0
export RETRO_FX2_PID=03ef
!! Carefully read the disclaimer about usage of USB VID/PID numbers !!
!! in the file README_USB-VID-PID.txt. You'll be responsible for any !!
!! misuse of the defaults provided with the project sources. !!
!! Usage of this VID/PID in any commercial product is forbidden. !!
3. Setup USB access -------------------------------------------------------
For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
Atlys boards 'udev' rules must be setup to allow user level access to
these devices. A set of rules is provided under
$RETROBASE/tools/fx2/sys
Follow the 'README.txt' file in this directory.
Notes:
- the provided udev rules use the VID/PID for 'internal lab use' as
described above. If other VID/PID used the file must be modified.
- your user account must be in group 'plugdev' (should be the default).
4. Rebuild Cypress FX2 firmware -------------------------------------------
The download includes pre-build firmware images for the Cypress FX2
USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.
These firmware images are under
$RETROBASE/tools/fx2/bin
To re-build them, e.g. because a different USB VID/PID is to be used
cd $RETROBASE/tools/fx2/src
make clean
make
make install
Note: The default build assumes that sdcc with a version 3.x is installed.
In case sdcc 2.x is installed use
make SDCC29=1
instead. See also tools/fx2/src/README.txt in the
Please read README_USB_VID-PID.txt carefully to understand the usage
of USB VID and PID.

22
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@@ -1,4 +1,4 @@
# $Id: INSTALL_ghdl.txt 537 2013-10-06 09:06:23Z mueller $
# $Id: INSTALL_ghdl.txt 651 2015-02-26 21:32:15Z mueller $
The w11 project uses the open source VHDL simulator
@@ -6,18 +6,18 @@ The w11 project uses the open source VHDL simulator
It used to be part of most distributions. Unfortunately the Debian maintainer
for ghdl refused at some point to integrate ghdl into Debian Etch. Therefore
ghdl was part of Debian Lenny, and again of Debian Squeeze, and is missing
again in Debian Wheezy (the current 'stable').
ghdl was part of Debian 5 "Lenny", and again of Debian 6 "Squeeze", and is
missing again in Debian 7 "Wheezy" (the current 'stable').
The glitch at Debian unfortunately lead to the removal of ghdl from Ubuntu,
which is based on Debian. Ubuntu Lucid (10.04) and up to Oneiric (11.10)
included ghdl, the currently maintained versions Precise (12.04 LTS) and
alter don't.
which is based on Debian. Ubuntu 10.04 "Lucid" up to 11.10 "Oneiric" included
ghdl, the currently maintained versions 12.04 LTS "Precise", 14.04 LTS "Trusty"
and 14.10 "Utopic" unfortunately don't.
To install ghdl on an up-to-date Debian or Ubuntu systems you have the
following options {as of early October 2013}:
following options {as of early February 2015}:
- Ubuntu Precise, Quantal, and Raring
- Ubuntu Precise and Trusty
Thanks to Peter Gavin Ubuntu packages for GHDL are available from his PPA
'Personal Package Archives', see
@@ -39,9 +39,9 @@ following options {as of early October 2013}:
There are also Ubuntu packages, but Joris focus is clearly on Debian.
Only Debian and Ubuntu are actively used by the w11a developer. The
situation for other linux distributions is therefore just taken from
the respective web sites:
Only Debian and Ubuntu are actively used by the w11a developer. The situation
for other Linux distributions is therefore just taken from the respective web
sites {status October 2013}:
- Suse
For Suse 12.2 and 12.3 un-official ghdl packages are available, but they

150
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@@ -1,4 +1,4 @@
$Id: README.txt 614 2014-12-20 15:00:45Z mueller $
$Id: README.txt 655 2015-03-04 20:35:21Z mueller $
Release notes for w11a
@@ -21,6 +21,152 @@ Release notes for w11a
2. Change Log ----------------------------------------------------------------
- trunk (2015-03-01: svn rev 29(oc) 655(wfjm); untagged w11a_V0.64) +++++++++
- Preface
- The w11 project started on a Spartan-3 based Digilent S3board, and soon
moved on to a Nexys2 with much better connectivity. Next step was the
Spartan-6 based Nexys3. Now is time to continue with 7-Series FPGAs.
- When Vivado started in 2013 it was immediately clear that the architecture
is far superior to ISE. But tests with the first versions were sobering,
the w11a design either didn't compile at all, or produced faulty synthesis
results. In 2014 Vivado matured, and the current version 2014.4 works
fine with the w11a code base.
- The original Nexys4 board allowed to quickly port Nexys3 version because
both have the same memory chip. The newer Nexys4 DDR will be addressed
later.
- The BRAM capacity of FPGAs increased significantly over time. The low
cost Basys3 board with the second smallest Artix-7 (XC7A35T) has 200 KB
BRAM. That allows to implement a purely BRAM based w11a system with
176 kB memory. Not enough for 2.11BSD, but for many other less demanding
OS available for a PDP11.
- The Nexyx4 and Basys3 have 16 LEDs. Not quite the 'blinking lights'
console of the classic 11/45 and 11/70, but enough to display the
well known OS typical light patterns the veterans remember so well.
- With a new design tool, a new FPGA generation, two new boards, and a
new interface for the rlink connection that some of the code and tools
base had to be re-organized.
- Last but not least: finally access to a bit bigger disks: RL11 support
- Many changes, some known issues, some rough edges may still lurke around
- Summary
- added support for Vivado
- added support for Nexys4 and Basys3 boards
- added RL11 disk support
- lots of documentation updated
- New features
- new directory trees for
- rtl/bplib/basys3 - support for Digilent Basys3 board
- rtl/bplib/nexys4 - support for Digilent Nexys4 board
- rtl/make_viv - make includes for Vivado
- new files
- tools/bin/xviv_ghdl_unisim - ghdl compile Vivado UNISIM & UNIMACRO libs
- new modules
- rtl/ibus/ibdr_rl11 - ibus controller for RL11
- rtl/vlib/rlink/ioleds_sp1c - io activity leds for rlink+serport_1clk
- rtl/vlib/xlib
- s7_cmt_sfs_gsim - Series-7 CMT: simple vhdl model
- s7_cmt_sfs_unisim - Series-7 CMT: wrapper for UNISIM
- rtl/w11a
- pdp11_bram_memctl - simple BRAM based memctl
- pdp11_dspmux - mux for hio display
- pdp11_ledmux - mux for hio leds
- pdp11_statleds - status led generator
- tools/src/librw11/
- Rw11*RL11 - classes for RL11 disk handling
- tools/src/librwxxtpp
- RtclRw11*RL11 - tcl iface for RL11 disk handling
- new systems
- rtl/sys_gen/tst_rlink - rlink tester
- basys3/sys_tst_rlink_b3 - for Basys3
- nexys4/sys_tst_rlink_n4 - for Nexys4
- rtl/sys_gen/tst_serloop - serport loop tester
- nexys4/sys_tst_serloop_n4 - for Nexys4
- rtl/sys_gen/tst_snhumanio - human I/O tester
- basys3/sys_tst_snhumanio_b3 - for Basys3
- nexys4/sys_tst_snhumanio_n4 - for Nexys4
- rtl/sys_gen/w11a - w11a
- basys3/sys_w11a_b3 - small BRAM only (176 kB memory)
- nexys4/sys_w11a_n4 - with full 4 MB memory using cram
- new oskits
- tools/oskit/211bsd_rl - new oskit for 2.11BSD on RL02
- tools/oskit/rt11-53_rl - new oskit for RT11 V5.3 on RL02
- tools/oskit/xxdp_rl - new oskit for XXDP 22 and 25 on RL02
- Changes
- renames
- ensure that old ISE and new Vivado co-exists, ensure telling names
- rtl/make -> make_ise
- rtl/bplib/bpgen/sn_4x7segctl -> sn_7segctl
- tools/bin/isemsg_filter -> xise_msg_filter
- tools/bin/xilinx_ghdl_unisim -> xise_ghdl_unisim
- tools/bin/xilinx_ghdl_simprim -> xise_ghdl_simprim
- retired files
- rtl/bplib/fx2lib
- fx2_2fifoctl_as - obsolete, wasn't actively used since long
- tools/bin
- set_ftdi_lat - obsolete, since kernel 2.6.32 the default is 1 ms
- xilinx_vhdl_chop - obsolete, since ISE 11 sources come chopped
- functional changes
- $RETROBASE/Makefile - re-structured, many new targets
- rtl/bplib/bpgen
- sn_7segctl - handle also 8 digit displays
- sn_humanio - configurable SWI and DSP width
- sn_humanio_rbus - configurable SWI and DSP width
- rtl/vlib/serport
- serport_1clock - export fractional part of divider
- rtl/ibus
- ibdr_maxisys - add RL11 (ibdr_rl11)
- rtl/sys_gen/w11a/*
- sys_w11a_* - use new led and dsp control modules
- tools/src/librlink
- RlinkConnect - drop LogOpts, indivitual getter/setter
- RlinkPortTerm - support custom baud rates (5M,6M,10M,12M)
- tools/src/librtcltools
- RtclGetList - add '?' (key list) and '*' (kv list)
- RtclSetList - add '?' (key list)
- RlogFile - Open(): now with cout/cerr support
- tools/src/librlinktpp
- RtclRlinkConnect - drop config cmd, use get/set cmd
- RtclRlinkPort - drop config cmd, use get/set cmd
- tools/src/librw11
- Rw11Rdma - PreExecCB() with nwdone and nwnext
- Rw11UnitDisk - add Nwrd2Nblk()
- tools/src/librwxxtpp
- RtclRw11CntlFactory - add RL11 support
- tools/bin
- xise_ghdl_unisim - handle also UNIMACRO lib
- vbomconv - handle Vivado flows too
- Bug fixes
- tools/src/librw11
- Rw11CntlRK11 - revise RdmaPostExecCB() logic
- Known issues
- V0.64-7: ghdl simulated OS boots via ti_w11 (-n4 ect options) fail due to
a flow control issue (likely since V0.63).
- V0.64-6: IO delays still unconstraint in vivado. All critical IOs use
explicitly IOB flops, thus timing well defined.
- V0.64-5: w11a_tb_guide.txt covers only ISE based tests (see also V0.64-4).
- V0.64-4: No support for the Vivado simulator (xsim) yet. With ghdl only
functional simulations, post synthesis (_ssim) fails to compile.
- V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud
is not supported according to FTDI, but works. 12 MBaud in next release.
- V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack
round trip times. Will be overcome by libusb based custom driver.
- V0.64-1: The large default transfer size for disk accesses leads to bad
throughput in the DL11 emulation for low speed links, like the
460kBaud the S3board is limited too. Will be overcome by a DL11
controller with more buffering.
- V0.62-2: rlink v4 error recovery not yet implemented, will crash on error
- V0.62-1: Command lists aren't split to fit in retransmit buffer size
{last two issues not relevant for w11 backend over USB usage because
the backend produces proper command lists and the USB channel is
usually error free}
- trunk (2015-01-04: svn rev 28(oc) 629(wfjm); untagged w11a_V0.63) +++++++++
- Summary
@@ -214,5 +360,5 @@ Release notes for w11a
- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
- just for fun: iist (not fully implemented and tested yet)
- two complete system configurations with
- for a Digilent S3BOARD rtl/sys_gen/w11a/s3board/sys_w11a_s3
- for a Digilent S3board rtl/sys_gen/w11a/s3board/sys_w11a_s3
- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2

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# $Id: README_buildsystem_ISE.txt 651 2015-02-26 21:32:15Z mueller $
Guide to the Build System (Xilinx ISE Version)
Table of content:
1. Concept
2. Setup system environment
a. Setup environment variables
b. Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl
3. Building test benches
a. With ghdl
b. With ISE ISim
4. Building systems
5. Configuring FPGAs (via make flow)
6. Configuring FPGAs (directly via config_wrapper)
7. Note on Artix-7 based designs
1. Concept ----------------------------------------------------------------
This projects uses GNU make to
- generate bit files (synthesis with xst and place&route with par)
- generate test benches (with ghdl or Xilinx ISim)
- configure the FPGA (with Xilinx Impact or Linux jtag)
The Makefile's in general contain only a few definitions, all the make logic
is concentrated in a few master makefiles which are included.
Simulation and synthesis tools usually need a list of the VHDL source
files, often in proper compilation order (libraries before components).
The different tools have different formats of these 'project files'.
The build system employed in this project is based on manifest files called
'vbom' or "VHDL bill of material" files
which list for each vhdl source file the libraries and sources for the
instantiated components, the later via their vbom, and last but not least
the name of the vhdl source file.
All file name are relative to the current directory. A recursive traversal
through all vbom's gives for each vhld module all sources needed to compile
it. The vbomconv script in tools/bin does this, and generates depending on
options
- make dependency files
- ISE xst project files (synthesis)
- ISE ISim project files (simulation)
- ghdl commands for analysis, inspection and make step
The master make files contain pattern rules like
%.ngc : %.vbom -- synthesize with xst
% : %.vbom -- build functional model test bench
which encapsulate all the vbomconv magic
A full w11a system is build from about 100 source files, test benches
from even more. Using the vbom's a large number of designs can be easily
maintained.
For more details on vbomconv consult the man page.
2. Setup system environment -----------------------------------------------
2a. Setup environment variables --------------------------------------
The build flows require the environment variables:
- RETROBASE: must refer to the installation root directory
- XTWI_PATH: install path of the ISE version, without /ISE_DS/ !
- RETRO_FX2_VID and RETRO_FX2_PID: default USB VID/PID for Cypress FX2
For general instructions on environment see INSTALL.txt .
For details on RETRO_FX2_VID and RETRO_FX2_PID see INSTALL_fx2.txt.
Notes:
- The build system uses a small wrapper script called xtwi to encapsulate
the Xilinx environment. It uses XTWI_PATH to setup the ISE environment on
the fly. For details consult 'man xtwi'.
- don't run the ISE setup scripts ..../settings(32|64).sh in your working
shell. Setup only XTWI_PATH !
2b. Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl ---------------
A few entities use UNISIM or UNIMACRO primitives, and models derived after
the par step require also SIMPRIM primitives. In these cases ghdl has to
link against a compiled UNISIM, UNIMACRO or SIMPRIM libraries.
To make handling of the parallel installation of several ISE versions
easy the compiled libraries are stored in sub-directories under $XILINX:
$XILINX/ghdl/unisim
$XILINX/ghdl/unimacro
$XILINX/ghdl/simprim
Two helper scripts will create these libraries:
cd $RETROBASE
xise_ghdl_unisim # does UNISIM and UNIMACRO
xise_ghdl_simprim # does SIMPRIM
Run these scripts for each ISE version which is installed.
3. Building test benches --------------------------------------------------
The build flows support two simulators
- ghdl -> open source, with VHPI support, doesn't accept sdf files
- ISE ISim -> limited to 50k lines in WebPack, no VHPI support
3a. With ghdl --------------------------------------------------------
To compile a ghdl based test bench named <tbench> all is needed is
make <tbench>
The make file will use <tbench>.vbom, create all make dependency files,
and generate the needed ghdl commands.
In many cases the test benches can also be compiled against the gate
level models derived after the xst, map or par step. To compile them
make ghdl_tmp_clean
make <tbench>_ssim # for post-xst
make <tbench>_fsim # for post-map
make <tbench>_tsim # for post-par
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
Notes:
- the post-xst simulation (_ssim targets) proved to be a valuable tool.
- ghdl fails to read sdf files generated by Xilinx tools, and thus does
not support a post-par simulation with full timing.
- post-par simulations without timing annotation often fail, most likely
due to clocking and delta cycle issues due to inserted clock buffers.
3b. With ISE ISim ----------------------------------------------------
To compile a ISE ISim based test bench named <tbench> all is needed is
make <tbench>_ISim
The make file will use <tbench>.vbom, create all make dependency files,
and generate the needed ISE ISim project files and commands.
In many cases the test benches can also be compiled against the gate
level models derived after the xst, map or par step. To compile them
make ise_tmp_clean
make <tbench>_ISim_ssim # for post-xst
make <tbench>_ISim_fsim # for post-map
make <tbench>_ISim_tsim # for post-par
Notes:
- ISim in ISE WebPack is limited to about 50k lines source code. That is
enough for many functional simulations, a w11a system has about 27k lines,
the test bench adds another 3k lines. But the limit gets quickly exceeded
with post-xst and especially post-par models. If the limit is exceeded, the
simulation engine throttles to snails speed.
- ISim does not support VHPI (interfacing of external C routines to VHDL).
Since VHPI is used in the rlink simulation all system test benches with
an rlink interface, thus most, will only run with ghdl and not with ISim.
4. Building systems -------------------------------------------------------
To generate a bit file for a system named <sys> all is needed is
make <sys>.bit
The make file will use <sys>.vbom, create all make dependency files, build
the ucf file with cpp, and run the synthesis flow (xst, ngdbuild, par, trce).
The log files will be conveniently renamed
<sys>_xst.log # xst log file
<sys>_tra.log # translate (ngdbuild) log file (renamed %.bld)
<sys>_map.log # map log file (renamed %_map.mrp)
<sys>_par.log # par log file (renamed %.par)
<sys>_pad.log # pad file (renamed %_pad.txt)
<sys>_twr.log # trce log file (renamed %.twr)
<sys>_tsi.log # trce tsi file (renamed %.tsi)
<sys>_bgn.log # bitgen log file (renamed %.bgn)
If only the xst or par output is wanted just use
make <sys>.ngc
make <sys>.ncd
Some tools require a .svf rather than a .bit file. It can be created with
make <sys>.svf
A simple 'message filter' system is also integrated into the make build flow.
For many (though not all) systems a .mfset file has been provided which
defines the xst,par and bitgen messages which are considered ok. To see
only the remaining message extracted from the various .log files simply
use the make target
make <sys>.mfsum
after a re-build.
5. Configuring FPGAs (via make flow) --------------------------------------
The make flow supports also loading the bitstream into FPGAs, either
via Xilinx Impact, or via the Cypress FX2 USB controller is available.
For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
simply use
make <sys>.iconfig
For using the Cypress FX2 USB controller on Digilent Nexys2, Nexys3 and
Atlys boards just connect the USB cable and
make <sys>.jconfig
This will automatically check and optionally re-load the FX2 firmware
to a version matching the FPGA design, generate a .svf file from the
.bit file, and configure the FPGA. In case the bit file is out-of-date
the whole design will be re-implemented before.
6. Configuring FPGAs (directly via config_wrapper) -------------------------
The make flow described above uses two scripts
config_wrapper # must be used with xtwi !
fx2load_wrapper
which can be used directly for loading available bit or svf files into
the FPGA. For detailed documentation see the respective man pages.
7. Note on Artix-7 based designs ------------------------------------------
The development for Nexys4 started with ISE, but has now fully moved to
Vivado. The make files for the ISE build flows have been kept for comparison
are have the name Makefile.ise. So for some Nexys4 designs and associated
one can still start with a
make -f Makefile.ise <target>
an ISE based build. To be used for tool comparisons, the ISE generated bit
files were never tested in an FPGA.

190
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@@ -0,0 +1,190 @@
# $Id: README_buildsystem_Vivado.txt 651 2015-02-26 21:32:15Z mueller $
Guide to the Build System (Xilinx Vivado Version)
Table of content:
1. Concept
2. Setup system environment
a. Setup environment variables
b. Compile UNISIM/UNIMACRO libraries for ghdl
3. Building test benches
a. With ghdl
4. Building systems
5. Configuring FPGAs (via make flow)
6. Note on ISE
1. Concept ----------------------------------------------------------------
This projects uses GNU make to
- generate bit files (with Vivado synthesis)
- generate test benches (with ghdl or Vivado XSim)
- configure the FPGA (with Vivado hardware server)
The Makefile's in general contain only a few definitions. By far most of
the build flow logic in Vivado is in tcl scripts, only a thin interface
layer is needed at the make level, which is concentrated in a few master
makefiles which are included.
Simulation and synthesis tools usually need a list of the VHDL source
files, sometimes in proper compilation order (libraries before components).
The different tools have different formats of these 'project descriptions.
The build system employed in this project is based on manifest files called
'vbom' or "VHDL bill of material" files
which list for each vhdl source file the libraries and sources for the
instantiated components, the later via their vbom, and last but not least
the name of the vhdl source file.
All file name are relative to the current directory. A recursive traversal
through all vbom's gives for each vhld module all sources needed to compile
it. The vbomconv script in tools/bin does this, and generates depending on
options
- make dependency files
- Vivado synthesis setup files
- Vivado simulation setup files
- ghdl commands for analysis, inspection and make step
The master make files contain pattern rules like
%.bit : %.vbom -- create bit file
% : %.vbom -- build functional model test bench
which encapsulate all the vbomconv magic
A full w11a system is build from about 100 source files, test benches
from even more. Using the vbom's a large number of designs can be easily
maintained.
For more details on vbomconv consult the man page.
2. Setup system environment -----------------------------------------------
2a. Setup environment variables --------------------------------------
The build flows require the environment variables:
- RETROBASE: must refer to the installation root directory
- XTWV_PATH: install path of the Vivado version
For general instructions on environment see INSTALL.txt .
Notes:
- The build system uses a small wrapper script called xtwv to encapsulate
the Xilinx environment. It uses XTWV_PATH to setup the Vivado environment
on the fly. For details consult 'man xtwv'.
- don't run the Vivado setup scripts ..../settings(32|64).sh in your working
shell. Setup only XTWV_PATH !
2b. Compile UNISIM/UNIMACRO libraries for ghdl -----------------------
A few entities use UNISIM or UNIMACRO primitives, and post synthesis models
require also UNISIM primitives. In these cases ghdl has to link against a
compiled UNISIM or UNIMACRO libraries.
To make handling of the parallel installation of several Vivado versions
easy the compiled libraries are stored in sub-directories under $XTWV_PATH:
$XTWV_PATH/ghdl/unisim
$XTWV_PATH/ghdl/unimacro
A helper scripts will create these libraries:
cd $RETROBASE
xviv_ghdl_unisim # does UNISIM and UNIMACRO
Run these scripts for each Vivado version which is installed.
Notes:
- Vivado supports SIMPRIM libraries only in Verilog form, there is no vhdl
version anymore.
- ghdl can therefore not be used to do timing simulations with Vivado.
However: under ISE SIMPRIM was available in vhdl, but ghdl did never accept
the sdf files, making ghdl timing simulations impossible under ISE too.
3. Building test benches --------------------------------------------------
The build flows currently supports only ghdl.
Support for the Vivado simulator XSim will be added in a future release.
3a. With ghdl --------------------------------------------------------
To compile a ghdl based test bench named <tbench> all is needed is
make <tbench>
The make file will use <tbench>.vbom, create all make dependency files,
and generate the needed ghdl commands.
In some cases the test benches can also be compiled against the gate
level models derived after the synthesis or optimize step. To compile them
make ghdl_tmp_clean
make <tbench>_ssim # for post synthesis {see Notes}
make <tbench>_osim # for post optimize {see Notes}
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
Notes:
- post synthesis or optimize models currently very often fail to compile
in ghdl due to a bug in the ghdl code generator.
4. Building systems -------------------------------------------------------
To generate a bit file for a system named <sys> all is needed is
make <sys>.bit
The make file will use <sys>.vbom, create all make dependency files and
starts Vivado in batch mode with the proper scripts which will handle the
build steps. The log files and reports are conveniently renamed
<sys>_syn.log # synthesis log (from runme.log)
<sys>_imp.log # implementation log (from runme.log)
<sys>_bit.log # write_bitstream log (from runme.log)
<sys>_syn_util.rpt # (from <sys>_utilization_synth.rpt)
<sys>_opt_drc.rpt # (from <sys>_opt_drc.rpt)
<sys>_pla_io.rpt # (from <sys>_io_placed.rpt)
<sys>_pla_clk.rpt # (from <sys>_clock_utilization_placed.rpt)
<sys>_pla_util.rpt # (from <sys>_utilization_placed.rpt)
<sys>_pla_cset.rpt # (from <sys>_control_sets_placed.rpt)
<sys>_rou_sta.rpt # (from <sys>_route_status.rpt)
<sys>_rou_drc.rpt # (from <sys>_drc_routed.rpt)
<sys>_rou_tim.rpt # (from <sys>_timing_summary_routed.rpt)
<sys>_rou_pwr.rpt # (from <sys>_power_routed.rpt)
<sys>_rou_util.rpt # (extra report_utilization)
<sys>_rou_util_h.rpt # (extra report_utilization -hierarchical)
<sys>_ds.rpt # (extra report_datasheet)
The design check points are also kept
<sys>_syn.dcp # (from <sys>.dcp)
<sys>_opt.dcp # (from <sys>_opt.dcp)
<sys>_pla.dcp # (from <sys>_placed.dcp)
<sys>_rou.dcp # (from <sys>_routed.dcp)
If only the post synthesis, optimize or route design checkpoints are wanted
make <sys>_syn.dcp
make <sys>_opt.dcp
make <sys>_rou.dcp
5. Configuring FPGAs ------------------------------------------------------
The make flow supports also loading the bitstream into FPGAs via the
Vivado hardware server. Simply use
make <sys>.vconfig
Note: works with Basys3 and Nexys4, only one board must connected.
6. Note on ISE ------------------------------------------------------------
The development for Nexys4 started with ISE, but has now fully moved to
Vivado. The make files for the ISE build flows have been kept for comparison
are have the name Makefile.ise. So for some Nexys4 designs and associated
one can still start with a
make -f Makefile.ise <target>
an ISE based build. To be used for tool comparisons, the ISE generated bit
files were never tested in an FPGA.

8
doc/man/man1/config_wrapper.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: config_wrapper.1 580 2014-08-10 15:47:10Z mueller $
.\" $Id: config_wrapper.1 651 2015-02-26 21:32:15Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -116,6 +116,9 @@ Cypress FX2 USB controller emulating an Altera USB-Blaster cable.
Path to current XILINX ISE installation. Required by all sub commands,
mainly to locate the \fI.bsdl\fP files which describe the JTAG commands
of all devices in the JTAG chain.
.br
Best is to use \fBconfig_wrapper\fP with the \fBxtwi\fP(1) wrapper, this will
automatically define this environment variable.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
@@ -131,7 +134,8 @@ Configures a Nexys3 board with \fItest.svf\fP using \fBjtag\fP(1).
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR jtag (1),
.BR fx2load_wrapper (1)
.BR fx2load_wrapper (1),
.BR xtwi (1)
.\" ------------------------------------------------------------------
.SH AUTHOR

67
doc/man/man1/set_ftdi_lat.1
View File

@@ -1,67 +0,0 @@
.\" -*- nroff -*-
.\" $Id: set_ftdi_lat.1 547 2013-12-29 13:10:07Z mueller $
.\"
.\" Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH SET_FTDI_LAT 1 2013-12-26 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
set_ftdi_lat \- set latency timer in FTDI USB UART or FIFO
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY set_ftdi_lat
.RI [ dev ]
.RI [ time ]
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBNote:\fP command is obsolete when kernel 2.6.32 or newer is used.
See NOTES section.
.
.PP
FTDI USB UART or FIFO adapters of type FT232, FT245, and other similar
models have a latency timer which controls the maximal time between reception
of a byte by the UART or FIFO and the emission of a USB frame. The default
is 16 msec on kernels prior to 2.6.32 and can lead to unsatisfactory
response times.
The
.B set_ftdi_lat
script allows to set this latency timer via a node in the \fI/sys\fP
virtual file system, specifically
.IP "" 4
.I /sys/bus/usb-serial/devices/ttyUSBn/latency_timer
.
.PP
The first optional argument \fIdev\fP allows to specify the device name
in the form \fIUSBn\fP with the default \fIUSB0\fP. The second optional
argument \fItime\fP allows to specify the new value of the latency timer,
given in msec. Default is 1 msec.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If device tty\fIdev\fP is not found or the entry in \fI/sys\fP is not
writable an exit status 1 is returned.
.\" ------------------------------------------------------------------
.SH EXAMPLES
In general the command is given via \fBsudo\fP(8) like
.EX
sudo set_ftdi_lat USB0 1
.EE
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR sudo (8)
.
.\" ------------------------------------------------------------------
.SH NOTES
For linux kernel 2.6.32 or newer the default is 1 ms already. On all
up-to-date systems therefore no need to use this command.
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

15
doc/man/man1/ti_rri.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: ti_rri.1 558 2014-06-01 22:20:51Z mueller $
.\" $Id: ti_rri.1 653 2015-03-01 12:53:01Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TI_RRI 1 2013-05-20 "Retro Project" "Retro Project Manual"
.TH TI_RRI 1 2015-01-28 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
ti_rri \- \fBRlink\fP Backend Server
@@ -103,7 +103,10 @@ serial port baud rate, default is '115k'. Allowed baud rate settings are:
460800, 460k, 500000, 500k, 921600, 921k,
1000000, 1000k, 1M, 1500000, 1500k,
2000000, 2000k, 2M, 2500000, 2500k,
3000000, 3000k, 3M, 4000000, 4000k, 4M
3000000, 3000k, 3M, 4000000, 4000k, 4M,
5000000, 5000k, 5M, 6000000, 6000k, 6M,
1000000, 10000k, 10M, 12000000, 12000k, 12M
.PD
.RE
.IP \fBopts\fP
@@ -197,6 +200,10 @@ with eval.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBti_rri --fifo --run='tbw tb_tst_rlink_n3'" 4
Starts the \fBghdl\fP(1) test bench 'tb_tst_rlink_n3' located in CWD via
\fBtbw\fP(1). It is assumed that the local \fItbw.dat\fP file configures
fifo communication for the test bench.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"

35
doc/man/man1/ti_w11.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: ti_w11.1 620 2014-12-25 10:48:35Z mueller $
.\" $Id: ti_w11.1 654 2015-03-01 18:45:38Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TI_W11 1 2013-05-20 "Retro Project" "Retro Project Manual"
.TH TI_W11 1 2015-02-22 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
ti_w11 \- Quick starter for \fBti_rri\fP with \fBw11\fP CPU designs
@@ -49,12 +49,18 @@ use /dev/ttyUSB* (* is device number \fIN\fP)
.RE
.
.SS "setup options for ghdl simulation runs"
.IP \fB-s3\fP
start \fItb_w11a_s3\fP simulation (w11a on S3BOARD)
.IP \fB-n2\fP
start \fItb_w11a_n2\fP simulation (w11a on Nexys2 board)
.PD 0
.IP \fB-b3\fP
start \fItb_w11a_b3\fP simulation (w11a on Basys3 board)
.IP \fB-n4\fP
start \fItb_w11a_n4\fP simulation (w11a on Nexys4 board)
.IP \fB-n3\fP
start \fItb_w11a_n3\fP simulation (w11a on Nexys3 board)
.IP \fB-n2\fP
start \fItb_w11a_n2\fP simulation (w11a on Nexys2 board)
.IP \fB-s3\fP
start \fItb_w11a_s3\fP simulation (w11a on S3board)
.PD
.
.SS "common options"
.IP \fB-e "\fR=\fIfile"\fR
@@ -65,9 +71,18 @@ it is assumed that they are in \fBlda\fP(5) format.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBti_w11 -u @211bsd_rk_boot.tcl\fR" 4
Assumes a FPGA board, with a \fBw11\fP CPU design already configured,
is connected via USB. \fBti_rri\fP(1) will be started and the given
boot script executed.
Assumes a FPGA board with a \fBw11\fP CPU design already configured.
Connected via USB, communication via Cypress FX2.
\fBti_rri\fP(1) will be started and the given boot script executed.
Typical way to start Nexys2 and Nexys3 boards.
.IP "\fBti_w11 -tu2,10M,break,cts @211bsd_rl_boot.tcl\fR" 4
Assumes a FPGA board with a \fBw11\fP CPU design already configured.
Connected via USB, communication via an USB UART. In this case the
device \fI/dev/ttyUSB2\fP will be used, with \fI10 MBaud\fP, \fIbreak\fP to
trigger auto-bauding, and \fIcts\fP to use hardware handshake.
\fBti_rri\fP(1) will be started and the given boot script executed.
Typical way to start Nexys4 boards.
.IP "\fBti_w11 -n3 -e $RETROBASE/tools/asm-11/w11/sys/dl11/simple_out.mac\fR"
Will start the \fItb_w11a_n3\fP test bench in \fBghdl\fP(1), on the fly

161
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@@ -1,12 +1,12 @@
.\" -*- nroff -*-
.\" $Id: vbomconv.1 558 2014-06-01 22:20:51Z mueller $
.\" $Id: vbomconv.1 646 2015-02-15 12:04:55Z mueller $
.\"
.\" Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\"
.\" ------------------------------------------------------------------
.
.TH VBOMCONV 1 2013-10-20 "Retro Project" "Retro Project Manual"
.TH VBOMCONV 1 2015-02-15 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbomconv \- generate files and actions from vbom manifest files
@@ -18,25 +18,19 @@ vbomconv \- generate files and actions from vbom manifest files
.
.SY vbomconv
.OP \-\-trace
.B \-\-dep_xst
|
.B \-\-dep_ghdl
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-dep_xst
|
.B \-\-dep_isim
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-xst_prj
|
.B \-\-isim_prj
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-ghdl_a_cmd
|
.B \-\-ghdl_a
.B \-\-dep_vsyn
.I vbom
.
.SY vbomconv
@@ -48,6 +42,15 @@ vbomconv \- generate files and actions from vbom manifest files
.
.SY vbomconv
.OP \-\-trace
.OP \-\-xlpath=\fIpath\fP
.B \-\-ghdl_a_cmd
|
.B \-\-ghdl_a
.I vbom
.
.SY vbomconv
.OP \-\-trace
.OP \-\-xlpath=\fIpath\fP
.B \-\-ghdl_m_cmd
|
.B \-\-ghdl_m
@@ -55,18 +58,30 @@ vbomconv \- generate files and actions from vbom manifest files
.
.SY vbomconv
.OP \-\-trace
.BI \-\-xst_export "\fR=\fPpath"
|
.BI \-\-ghdl_export "\fR=\fPpath"
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-xst_prj
|
.B \-\-isim_prj
.I vbom
.
.SY vbomconv
.OP \-\-trace
.BI \-\-xst_export "\fR=\fPpath"
|
.BI \-\-isim_export "\fR=\fPpath"
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-vsyn_prj
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-get_top
.I vbom
.
@@ -96,17 +111,19 @@ and top level design last.
The \fBvbomconv\fP tool does this traversal of \fBvbom\fP
files and generates, depending on command line options, the files and/or
commands needed to run a synthesis tool or to build a simulation model.
Currently supported is synthesis with ISE \fBxst\fP and simulation with
\fBghdl\fP(1) or ISE \fBISim\fP.
Currently supported is synthesis with Xilinx ISE \fBxst\fP Xilinx Vivado
and simulation with \fBghdl\fP(1) or Xilinx ISE \fBISim\fP.
\fBvbomconv\fP therefore currently generates
.PD 0
.IP "\fB- xst\fP" 8
project files
.IP "\fB- ghdl\fP" 8
commands for analysis, inspection and make step
.IP "\fB- xst\fP" 8
project files
.IP "\fB- ISim\fP" 8
project files
.IP "\fB- vsyn\fP" 8
project setups for Vivado synthesis
.IP "\fB- make\fP" 8
dependency files
.PD
@@ -183,7 +200,8 @@ stem of the \fIvbom\fP file name.
.
.IP "\fB@lib\fP:\fIname\fP"
allows to specify additional system libraries. Currently used to indicate
that the \fIunisim\fP or \fIsimprim\fP libraries are needed by \fBghdl\fP.
that the \fIunisim\fP, \fIunimacro\fP or \fIsimprim\fP libraries are
needed by \fBghdl\fP.
.
.IP "\fB@ucf_cpp\fP:\fIfile\fP"
indicates that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1)
@@ -213,6 +231,17 @@ of the vbom file traversal and processing, the process of source file ranking
to determine the compilation order, and of the final internal file list and
property table.
.
.\" ----------------------------------------------
.TP
.BI \-\-xlpath \fR=\fPpath
Defines the location where the \fBghdl\fP compiled Xilinx unisim, unimacro
or simprim libraries are located. This option is mandatory for
\fB\-\-ghdl_a\fP and \fB\-\-ghdl_m\fP commands when the design contains
a \fB@lib\fP directive.
These compiled libs are typically created with the
\fBxise_ghdl_unisim\fP(1) or \fBxise_ghdl_simprim\fP(1) commands.
.
.\" --------------------------------------------------------
.SH ACTIONS
.P
.\" ----------------------------------------------
@@ -222,16 +251,26 @@ one not requiring a \fIvbom\fP file.
.
.\" ----------------------------------------------
.TP
.B \-\-dep_xst
.TQ
.B \-\-dep_ghdl
.TQ
.B \-\-dep_xst
.TQ
.B \-\-dep_isim
These three actions write to \fIstdout\fP dependency rules for inclusion in
.TQ
.B \-\-dep_vsyn
These four actions write to \fIstdout\fP dependency rules for inclusion in
\fIMakefile\fPs.
Together with an appropruate pattern rule they allow to automatitize
the dependency handling, see the EXAMPLES section for practical usage.
\fB\-\-dep_ghdl\fP creates the dependencies for \fBghdl\fP
based simulation models and produces the following types of dependencies
.EX
\fI<stem>\fP : \fI<stem>\fP.dep_ghdl
\fI<stem>\fP : \fB*\fP.vhd
\fI<stem>\fP.dep_ghdl : \fB*\fP.vbom
.EE
\fB\-\-dep_xst\fP creates the dependencies for \fBxst\fP
synthesis make flows and produces the following types of dependencies
.EX
@@ -258,14 +297,6 @@ for example
sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp
.EE
\fB\-\-dep_ghdl\fP creates the dependencies for \fBghdl\fP
based simulation models and produces the following types of dependencies
.EX
\fI<stem>\fP : \fI<stem>\fP.dep_ghdl
\fI<stem>\fP : \fB*\fP.vhd
\fI<stem>\fP.dep_ghdl : \fB*\fP.vbom
.EE
\fB\-\-dep_isim\fP creates the dependencies for ISE \fBISim\fP
based simulation models and produces the following types of dependencies
.EX
@@ -273,26 +304,16 @@ based simulation models and produces the following types of dependencies
\fI<stem>\fP_ISim : \fB*\fP.vhd
\fI<stem>\fP.dep_isim : \fB*\fP.vbom
.EE
.
.\" ----------------------------------------------
.TP
.B \-\-xst_prj
.TQ
.B \-\-isim_prj
These two actions write to \fIstdout\fP a project file suitable for ISE
\fBxst\fP or \fBISim\fP, respectively.
The vhdl source files are in proper compilation order. See
the EXAMPLES section for practical usage in a make flow.
.
.\" ----------------------------------------------
.TP
.B \-\-ghdl_a_cmd
.TQ
.B \-\-ghdl_a
The \fB\-\-ghdl_a_cmd\fP action writes to \fIstdout\fP a list of
\fB"ghdl -a"\fP commands for the \fBghdl\fP analysis step.
The commands are in proper compilation order. The \fB\-\-ghdl_a\fP
action immediately executes these commands via \fBexec\fP(3).
\fB\-\-dep_vsyn\fP creates the dependencies for Vivado synthesis make flows
and produces the following types of dependencies
.EX
\fI<stem>\fP.bit : \fI<stem>\fP.dep_vsyn
\fI<stem>\fP.bit : \fB*\fP.vhd \fB*\fP.xdc
\fI<stem>\fP_syn.dcp : \fB*\fP.vhd \fB*\fP.xdc
\fI<stem>\fP_rou.dcp : \fB*\fP.vhd \fB*\fP.xdc
\fI<stem>\fP.dep_vsyn : \fB*\fP.vbom
.EE
.
.\" ----------------------------------------------
.TP
@@ -306,6 +327,16 @@ action immediately executes this command via \fBexec\fP(3).
.
.\" ----------------------------------------------
.TP
.B \-\-ghdl_a_cmd
.TQ
.B \-\-ghdl_a
The \fB\-\-ghdl_a_cmd\fP action writes to \fIstdout\fP a list of
\fB"ghdl -a"\fP commands for the \fBghdl\fP analysis step.
The commands are in proper compilation order. The \fB\-\-ghdl_a\fP
action immediately executes these commands via \fBexec\fP(3).
.
.\" ----------------------------------------------
.TP
.B \-\-ghdl_m_cmd
.TQ
.B \-\-ghdl_m
@@ -317,6 +348,24 @@ The \fB\-\-ghdl_m\fP action immediately executes this command via
.
.\" ----------------------------------------------
.TP
.B \-\-xst_prj
.TQ
.B \-\-isim_prj
These two actions write to \fIstdout\fP a project file suitable for ISE
\fBxst\fP or \fBISim\fP, respectively.
The vhdl source files are in proper compilation order. See
the EXAMPLES section for practical usage in a make flow.
.
.\" ----------------------------------------------
.TP
.B \-\-vsym_prj
This action write to \fIstdout\fP a Tcl script suitable as project definition
for Vivado synthesis. This script is source'ed or eval'ed and defines the
source fileset and the constraints fileset. The vhdl source files are in
proper compilation order.
.
.\" ----------------------------------------------
.TP
.BI \-\-xst_export \fR=\fPpath
.TQ
.BI \-\-ghdl_export \fR=\fPpath
@@ -388,7 +437,7 @@ of the GNU \fBmake\fP(1) \fIinclude\fP directive to fully automatize the
proper generation of dependencies.
Just add to the \fIMakefile\fP
a pattern rule to create the dependency rule files from the \fBvbom\fP
files and include them. In case they don't yet exists or are out of date
files and include them. In case they don't yet exist or are out of date
\fBmake\fP(1) will (re-)create them and restart. Example for using
\fB\-\-dep_xst\fP in a \fIMakefile\fP :
.PP
@@ -461,8 +510,8 @@ output like in
.BR xtwi (1),
.BR cpp (1),
.br
.BR xilinx_ghdl_simprim (1),
.BR xilinx_ghdl_unisim (1)
.BR xise_ghdl_simprim (1),
.BR xise_ghdl_unisim (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR

67
doc/man/man1/xilinx_ghdl_unisim.1
View File

@@ -1,67 +0,0 @@
.\" -*- nroff -*-
.\" $Id: xilinx_ghdl_unisim.1 522 2013-05-24 17:50:29Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XILINX_GHDL_UNISIM 1 2010-07-25 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xilinx_ghdl_unisim \- compile Xilinx ISE UNISIM libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xilinx_ghdl_unisim
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBxilinx_ghdl_unisim\fP compiles the Xilinx ISE/WebPack UNISIM libraries for
\fBghdl\fP. The object files generated by \fBghdl\fP
are stored in the directory tree of the currently active version of
ISE/WebPack under \fI$XILINX/ghdl/unisim\fP.
This is convenient when several ISE/WebPack versions are installed in
parallel, the \fB$XILINX\fP
environment variable is enough to setup the context for the synthesis
flows as well as for build of \fBghdl\fP models. Just use the
\fBghdl\fP option
.EX
-P${XILINX}/ghdl/unisim
.EE
to link to the UNISIM library.
Up to ISE 10 the VITAL models were all concatinated in one large file
\fIunisim_VITAL.vhd\fP. In this case the \fBxilinx_vhdl_chop\fP
helper script will create individual source files for each model.
For ISE 11 and later the modules are shipped as separate files.
The XILINX source code has since many releases some buggy statements with
self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.IP \fBXILINX\fP
points to the root of the currently active ISE/WebPack installation.
.
.\" ------------------------------------------------------------------
.SH FILES
.IP \fI$XILINX/vhdl/src/unisims\fP
The vhdl sources for the UNISIM library are looked for in this directory tree.
.IP \fI$XILINX/ghdl/unisim\fP
The created object files will be written into this directory. The directory
is created if not yet existing. Note that the \fI$XILINX\fP
directory must be writable for the script.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ghdl (1),
.BR xilinx_ghdl_simprim (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

37
doc/man/man1/xilinx_ghdl_simprim.1 → doc/man/man1/xise_ghdl_simprim.1
View File

@@ -1,34 +1,35 @@
.\" -*- nroff -*-
.\" $Id: xilinx_ghdl_simprim.1 522 2013-05-24 17:50:29Z mueller $
.\" $Id: xise_ghdl_simprim.1 639 2015-01-30 18:12:19Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XILINX_GHDL_SIMPRIM 1 2010-07-25 "Retro Project" "Retro Project Manual"
.TH XISE_GHDL_SIMPRIM 1 2015-01-29 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xilinx_ghdl_simprim \- compile Xilinx ISE SIMPRIM libraries for ghdl
xise_ghdl_simprim \- compile Xilinx ISE SIMPRIM libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xilinx_ghdl_simprim
.B xise_ghdl_simprim
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBxilinx_ghdl_simprim\fP compiles the Xilinx ISE/WebPack SIMPRIM libraries
\fBxise_ghdl_simprim\fP compiles the Xilinx ISE/WebPack SIMPRIM libraries
for \fBghdl\fP.
The object files generated by \fBghdl\fP are stored in the directory
tree of the currently active version of ISE/WebPack under
\fI$XILINX/ghdl/simprim\fP.
This is convenient when several ISE/WebPack versions are installed in
parallel, the \fB$XILINX\fP
environment variable is enough to setup the context for the synthesis
flows as well as for build of \fBghdl\fP models. Just use the \fBghdl\fP
option
Since direct calls to ISE tools are in general encapsulated with \fBxtwi\fP(1)
the \fI$XTWI_PATH\fP is used instead of \fI$XILINX\fP.
This allows to use this script and \fBghdl\fP without a \fBxtwi\fP wrapper.
Just use the \fBghdl\fP option
.EX
-P${XILINX}/ghdl/simprim
-P${XWTI_PATH}/ISE_DE/ISE/ghdl/unisim
.EE
to link to the SIMPRIM library.
@@ -39,7 +40,7 @@ In this case the \fBxilinx_vhdl_chop\fP
helper script will create individual source files for each model.
For ISE 11 and later the modules are shipped as separate files.
The XILINX source code has since many releases some buggy statements with
The Xilinx source code has since many releases some buggy statements with
self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
@@ -47,21 +48,21 @@ helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.TP
.B XILINX
.IP \fBXTWI_PATH\fP
points to the root of the currently active ISE/WebPack installation.
.
.\" ------------------------------------------------------------------
.SH FILES
.IP \fI$XILINX/vhdl/src/simprims\fP
.IP \fI$XTWI_PATH/ISE_DS/ISE/vhdl/src/simprims\fP
The vhdl sources for the SIMPRIM library are looked for in this directory tree.
.IP \fI$XILINX/ghdl/simprim\fP
.IP \fI$XTWI_PATH/ISE_DS/ISE/ghdl/simprim\fP
The created object files will be written into this directory. The directory
is created if not yet existing. Note that the \fI$XILINX\fP
is created if not yet existing. Note that the \fI$XTWI_PATH\fP
directory must be writable for the script.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xtwi (1),
.BR ghdl (1),
.BR xilinx_ghdl_unisim (1)
.

68
doc/man/man1/xise_ghdl_unisim.1 Normal file
View File

@@ -0,0 +1,68 @@
.\" -*- nroff -*-
.\" $Id: xise_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XISE_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xise_ghdl_unisim \- compile Xilinx ISE UNISIM and UNIMACRO libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xise_ghdl_unisim
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBxise_ghdl_unisim\fP compiles the Xilinx ISE UNISIM and UNIMACRO
libraries for \fBghdl\fP. The object files generated by \fBghdl\fP
are stored in the directory tree of the currently active version of
ISE under \fI$XILINX/ghdl/unisim\fP and \fI$XILINX/ghdl/unimacro\fP.
Since direct calls to ISE tools are in general encapsulated with \fBxtwi\fP(1)
the \fI$XTWI_PATH\fP is used instead of \fI$XILINX\fP.
This allows to use this script and \fBghdl\fP without a \fBxtwi\fP wrapper.
Just use the \fBghdl\fP option
.EX
-P${XWTI_PATH}/ISE_DE/ISE/ghdl/unisim
-P${XWTI_PATH}/ISE_DE/ISE/ghdl/unimacro
.EE
to link to the UNISIM or UNIMACRO library.
The Xilinx source code has since many releases some buggy statements with
self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.IP \fBXTWI_PATH\fP
points to the root of the currently active ISE installation.
.
.\" ------------------------------------------------------------------
.SH FILES
.IP \fI$XTWI_PATH/ISE_DS/ISE/vhdl/src/unisims\fP
The vhdl sources for the Xilinx ISE UNISIM library
.IP \fI$XTWI_PATH/ISE_DS/ISE/vhdl/src/unimacro\fP
The vhdl sources for the Xilinx ISE UNIMACRO library
.IP \fI$XTWI_PATH/ISE_DS/ISE/ghdl\fP
The created object files will be written into this directory. The directory
is created if not yet existing. Note that the \fI$XTWI_PATH\fP
directory must be writable for the script.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xtwi (1),
.BR ghdl (1),
.BR xise_ghdl_simprim (1),
.BR xviv_ghdl_unisim (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

22
doc/man/man1/isemsg_filter.1 → doc/man/man1/xise_msg_filter.1
View File

@@ -1,23 +1,23 @@
.\" -*- nroff -*-
.\" $Id: isemsg_filter.1 550 2014-02-03 08:16:57Z mueller $
.\" $Id: xise_msg_filter.1 640 2015-02-01 09:56:53Z mueller $
.\"
.\" Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.TH ISEMSG_FILTER 1 2014-01-02 "Retro Project" "Retro Project Manual"
.TH ISEMSG_FILTER 1 2015-01-30 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
isemsg_filter \- message filter for Xilinx ISE tool chain log files
xise_msg_filter \- message filter for Xilinx ISE tool chain log files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY isemsg_filter
.SY xise_msg_filter
.OP \-\-pack
.I TYPE
.I MFSET
.I LOGFILE
.
.SY isemsg_filter
.SY xise_msg_filter
.B \-\-help
.YS
.
@@ -28,12 +28,12 @@ Scans the log file \fILOGFILE\fP generated by Xilinx ISE tool specified
by \fITYPE\fP for informational, warning and error messages and compares
these messages against a set of message filter rules defined in the
\fIMFSET\fP file.
isemsg_filter will print all no-matching messages.
xise_msg_filter will print all no-matching messages.
All filter rules which do not match a message are also listed, these
messages are considered missing.
Matched messages are considered accepted.
In normal operation they will not create output.
isemsg_filter is useful for example in \fBmake\fP(1) based flows to
xise_msg_filter is useful for example in \fBmake\fP(1) based flows to
create a short summary from the log files.
The accepted values for \fITYPE\fP are:
@@ -72,7 +72,7 @@ print full help.
Simply a list of regular expression patters structured by section headers
of the form "[TYPE]".
Blank lines and lines starting with '#' will be ignored.
isemsg_filter will extract the patters of the section matching the
xise_msg_filter will extract the patters of the section matching the
\fITYPE\fP argument.
.SS Example message filter file
.EX
@@ -91,14 +91,14 @@ can't be opend an exit status 1 is returned.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBisemsg_filter xst proj.mfset proj_xst.log\fR" 4
.IP "\fBxise_msg_filter xst proj.mfset proj_xst.log\fR" 4
Generate a short summary of a ISE xst log file.
.
.\" ------------------------------------------------------------------
.SH "BUGS"
The \fIMFSET\fP file is flat, no structuring possible, e.g. with includes.
It be great to have for example default rules for each target device.
Since ISE is 'end-of-life' no further work on isemsg_filter will be done.
Since ISE is 'end-of-life' no further work on xise_msg_filter will be done.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"

12
doc/man/man1/xtwi.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: xtwi.1 558 2014-06-01 22:20:51Z mueller $
.\" $Id: xtwi.1 651 2015-02-26 21:32:15Z mueller $
.\"
.\" Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -47,6 +47,16 @@ $XTWI_PATH/ISE_DS/settings64.sh
ISE setup script located and sourced on 32 or 64 bit systems
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBxtwi netgen -sim -intstyle xflow -ofmt vhdl -w test.ngc" 4
Starts the ISE netlister and generates a vhdl model from \fItest.ngc\fP.
.
.\" ------------------------------------------------------------------
.SH "NOTES"
If both ISE and Vivado are used \fBxtwi\fP and \fBxtwv\fP(1) offer a convenient
way to have both tools available in one session without interference.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xtwv (1)
.

17
doc/man/man1/xtwv.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: xtwv.1 558 2014-06-01 22:20:51Z mueller $
.\" $Id: xtwv.1 651 2015-02-26 21:32:15Z mueller $
.\"
.\" Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -18,7 +18,7 @@ xtwv \- Xilinx Tool Wrapper script for Vivado
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
The Xilinx Vivado setup script redefines PATH and potentially LD_LIBRARY_PATH.
The Xilinx Vivado setup script redefines PATH and LD_LIBRARY_PATH.
The Vivado tools run fine in this environment, but other installed programs
on the system might fail. \fBxtwv\fP helps to keep the Vivado environment
separate from the normal working environment.
@@ -46,6 +46,19 @@ $XTWV_PATH/settings64.sh
Vivado setup script located and sourced on 32 or 64 bit systems
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBxtwv vivado -mode batch -source test.tcl" 4
Starts vivado in batch mode and executes the script \fItest.tcl\fP.
.
.\" ------------------------------------------------------------------
.SH "NOTES"
Vivado is a lot less intrusive as ISE, but it's still a good precaution to
wrap calls of Vivado tools with \fBxtwv\fP.
.br
If both Vivado and ISE are used \fBxtwv\fP and \fBxtwi\fP(1) offer a convenient
way to have both tools available in one session without interference.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xtwi (1)
.

67
doc/man/man1/xviv_ghdl_unisim.1 Normal file
View File

@@ -0,0 +1,67 @@
.\" -*- nroff -*-
.\" $Id: xviv_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $
.\"
.\" Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XVIV_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xviv_ghdl_unisim \- compile Xilinx Vivado UNISIM and UNIMACRO libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xviv_ghdl_unisim
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBxviv_ghdl_unisim\fP compiles the Xilinx Vivado UNISIM and UNIMACRO
libraries for \fBghdl\fP. The object files generated by \fBghdl\fP
are stored in the directory tree of the currently active version of
Vivado under \fI$XTWV_PATH/ghdl/unisim\fP and \fI$XTWV_PATH/ghdl/unimacro\fP.
This script build the 'retarget' version of UNISIM, thus most legacy entities
from the ISE UNISIM library are available and will be mapped to the matching
Series-7 entities.
Just use the \fBghdl\fP option
.EX
-P${XWTI_PATH}/ghdl/unisim
-P${XWTI_PATH}/ghdl/unimacro
.EE
to link to the UNISIM or UNIMACRO library.
\fBghdl\fP can be used without a \fBxtwv\fP wrapper.
The Xilinx source code has since many releases some buggy statements with
self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.IP \fBXTWV_PATH\fP
points to the root of the currently active Vivado installation.
.
.\" ------------------------------------------------------------------
.SH FILES
.IP \fI$XTWV_PATH/data/vhdl/src/unisims\fP
The vhdl sources for the Xilinx Vivado UNISIM library
.IP \fI$XTWV_PATH/data/vhdl/src/unimacro\fP
The vhdl sources for the Xilinx Vivado UNIMACRO library
.IP \fI$XTWV_PATH/ghdl\fP
The created object files will be written into this directory. The directory
is created if not yet existing. Note that the \fI$XTWV_PATH\fP
directory must be writable for the script.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xtwv (1),
.BR ghdl (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

34
doc/man/man5/vbom.5
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: vbom.5 558 2014-06-01 22:20:51Z mueller $
.\" $Id: vbom.5 646 2015-02-15 12:04:55Z mueller $
.\"
.\" Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH VBOM 2013-10-20 "Retro Project" "Retro Project Manual"
.TH VBOM 2015-02-15 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbom \- vhdl manifest file format - 'vhdl bill of material'
@@ -72,14 +72,18 @@ Currently supported \fItag\fP names are
.RS
.RS 3
.PD 0
.IP "\fBxst\fP" 6
included in conjunction with xst synthesis
.IP "\fBghdl\fP"
.IP "\fBghdl\fP" 6
included in conjunction with ghdl simulation
.IP "\fBisim\fP"
included in conjunction with isim simulation
.IP "\fBsim\fP"
included in conjunction with simulation (ghdl or isim)
.IP "\fBxst\fP" 6
included in conjunction with ISE xst synthesis
.IP "\fBisim\fP" 6
included in conjunction with ISE ISim simulation
.IP "\fBvsyn\fP" 6
included in conjunction with Vivado synthesis
.IP "\fBvsim\fP" 6
included in conjunction with Vivado simulation
.IP "\fBsim\fP" 6
included in conjunction with simulation (ghdl,isim,vsim)
.PD
.RE
.RE
@@ -114,13 +118,17 @@ from the stem of the \fBvbom\fP file name.
.
.IP "\fB@lib\fP:\fIname\fP"
Specifies an additional system library. Allowed values for \fIname\fP are
\fIunisim\fP and \fIsimprim\fP. Currently used to generate the appropriate
-L options for \fBghdl\fP commands, e.g. generated by the
\fBvbomconv\fP action \fB\-\-ghdl_m\fP.
\fIunisim\fP, \fIunimacro\fP and \fIsimprim\fP.
Currently used to generate the appropriate -L options for \fBghdl\fP commands,
e.g. generated by the \fBvbomconv\fP action \fB\-\-ghdl_m\fP.
.
.IP "\fB@ucf_cpp\fP:\fIfile\fP"
Specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1)
from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files.
.
.IP "\fB@xdc\fP:\fIfile\fP"
Specifies that \fIfile\fP is a constraint file for Vivado synthesis and should
be included in the constraints fileset.
.RE
.
.\" ------------------------------------------------------------------

170
doc/w11a_os_guide.txt
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@@ -1,4 +1,4 @@
# $Id: w11a_os_guide.txt 581 2014-08-10 21:48:46Z mueller $
# $Id: w11a_os_guide.txt 654 2015-03-01 18:45:38Z mueller $
Guide to run operating system images on w11a systems
@@ -14,59 +14,74 @@ Guide to run operating system images on w11a systems
1. I/O emulation setup ----------------------------------------------------
All UNIBUS peripherals which exchange data (currently DL11, LP11, PC11, RK11)
are currently emulated via a backend process. The communication between
FPGA board and backend server can be via
All UNIBUS peripherals which exchange data (currently DL11, LP11, PC11, RK11,
and RL11) are currently emulated via a backend process. The communication
between FPGA board and backend server can be via
- Serial port
- via an integrated USB-UART bridge
- on basys3 and nexys4 with a FT2232HQ, allows up to 12M Baud
- on nexys3 with a FT232R, allows up to 2M Baud
- via RS232 port, as on s3board and nexys2
- using a serial port (/dev/ttySx) is limited to 115 kBaud on most PCs.
- using a USB-RS232 adapter was tested up to 460k Baud.
- Direct USB connection using a Cypress FX2 USB controller
- is supported on the nexys2 and nexys3 FPGA boards
- much faster than serial port connections (see below)
- also allows to configure the FPGA over the same USB connection
- Serial port
- via direct (/dev/ttySx) or via a USB-RS232 adapter. A direct connection
is limited to 115k Baud on most PCs, while a connection via a USB-RS232
adapter was tested up to 460k Baud. A USB-RS232 adapter is thus highly
recommended
- via integrated USB-RS232 adapter, like on nexys3 board. This is much
faster, allows bitrates up to 2 M Baud.
Notes: - A USB-RS232 cable with a FTDI FT232R chip, like the cable offered
by FTDI as US232R-100 works fine.
- A USB-RS232 cable with a Prolific Technology PL2303 chip simply
never gave reliable connections for higher Baud rates.
- The rest assumes that a USB-RS232 cable with FTDI chip is used
- A 460k Baud connection gives in practice a disk throughput of
about 20 kB/s. This allows to test the system but is a bit slow
to real usage. In an OS with good disk caching like 2.11BSD the
impact of such a 'slow disk' is actually smaller than the bare
numbers suggest.
- On older linux kernels (prior 2.6.32) it is essential to set the
latency timer for the FTDI USB-RS232 cable to 1 ms (from the
power up default of 16 ms), e.g. with
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
For linux kernel 2.6.32 or newer the default is 1 ms already.
Notes:
- A 10M Baud connection, like on a nexys4, gives disk access rates and
throughputs much better than the real hardware of the 70's and is well
suitable for practical usage.
- In an OS with good disk caching like 2.11BSD the impact of disk speed
is actually smaller than the bare numbers suggest.
- A 460k Baud connection gives in practice a disk throughput of ~20 kB/s.
This allows to test the system but is a bit slow for real usage.
- USB-RS232 cables with a FTDI FT232R chip work fine, tests with Prolific
Technology PL2303 based cable never gave reliable connections for higher
Baud rates.
Recommended setup for best performance (boards ordered by vintage):
Board Channel/Interface nom. speed peak transfer rate
basys3 USB-UART bridge 10M Baud 910 kB/sec
nexys4 USB-UART bridge 10M Baud 910 kb/sec
nexys3 Cypress FX2 USB USB2.0 speed 30000 kB/sec
nexys2 Cypress FX2 USB USB2.0 speed 30000 kB/sec
s3board RS232+USB-RS232 cable 460k Baud 41 kB/sec
2. FPGA Board setup -------------------------------------------------------
- Using Cypress FX2 USB controller for configuration and rlink communication
- for nexys2
- connect USB cable to mini-USB connector (between RS232 and PS/2 port)
- for nexys3
- connect USB cable to micro-USB connector labeled 'USB PROG'
Recommended setups
- Using serial port for rlink communication
- for s3board and nexys2
- connect the USB-RS232 cable to the RS232 port
- for nexys3
- connect USB cable to the micro-USB connector 'UART'
(next to the 5 buttons)
- connect a JTAG programmer (e.g. Xilinx USB Cable II) to JTAG pins
- Basys3
- connect USB cable to micro-USB connector labeled 'PROG'
- to configure via vivado hardware server
make <sys>.vconfig
- Configure the FPGA
- if Cypress FX2 port is connected load design with
- Nexys4
- connect USB cable to micro-USB connector labeled 'PROG'
- to configure via vivado hardware server
make <sys>.vconfig
- Nexys3
- use Cypress FX for configure and and rlink communication
- connect USB cable to micro-USB connector labeled 'USB PROG'
- to configure via FX2 and jtag tool
make <sys>.jconfig
- otherwise use impact with
- Nexys2
- connect USB cable to mini-USB connector (between RS232 and PS/2 port)
- to configure via FX2 and jtag tool
make <sys>.jconfig
- S3board
- connect the USB-RS232 cable to the RS232 port
- connect a JTAG programmer (e.g. Xilinx USB Cable II) to JTAG pins
- to configure via ISE Impact
make <sys>.iconfig
3. Rlink and Backend Server setup -----------------------------------------
@@ -84,17 +99,55 @@ Guide to run operating system images on w11a systems
are in the indicated positions (SWI=...). The concrete boot script
name <boot-script> is given in the following sections
[for n2,n3 over fx2:]
SWI = 00000100
ti_w11 -u @<oskit-name>_boot.tcl
- for b3 over serial
SWI = 00000000 00101010
ti_w11 -tu<dn>,10M,break,xon @<oskit-name>_boot.tcl
[for s3,n2 over serial:]
SWI = 00000010
ti_w11 -tu0,460k,break,xon @<oskit-name>_boot.tcl
[for n3 over serial:]
SWI = 00000010
ti_w11 -tu0,2M,break,xon @<oskit-name>_boot.tcl
NOTE: the basys3 w11a has only 176 kB memory (all from BRAMS!)
unix-v5 works fine. XXDP, RT11 and RSX-11M should work.
211bsd will not boot, either most RSX-11M+ systems.
- for n4 over serial
SWI = 00000000 00101000
ti_w11 -tu<dn>,10M,break,cts @<oskit-name>_boot.tcl
- for n2,n3 over fx2
SWI = 00101100
ti_w11 -u @<oskit-name>_boot.tcl
- for s3 serial
SWI = 00101010
ti_w11 -tu<dn>,460k,break,xon @<oskit-name>_boot.tcl
Notes:
- on <dn>, the serial device number
- check with 'ls /dev/ttyUSB*' to see what is available
- <dn> is typically '1' if only a single basys3 or nexys4 is connected
Initially two ttyUSB devices show up, the lower is for FPGA config
and will disappear when Vivado hardware server is used once. The
upper provides the data connection.
- <dn> is typically '0' if only a single USB-RS232 cable is connected
- on LED display
- is controlled by SWI(3)
0 -> system status
1 -> DR emulation --> OS specific light patterns
- on Hex display
- is controlled by SWI(5:4)
- boards with a 4 digit display
00 -> serial link rate divider
01 -> PC
10 -> DISPREG
11 -> DR emulation
- boards with 8 digit display
- SWI(5) select for DSP(7:4) display
0 -> serial link rate divider
1 -> PC
- SWI(4) select for DSP(3:0) display
0 -> DISPREG
1 -> DR emulation
4. simh simulator setup ---------------------------------------------------
Sometimes it is good to compare the w11a behaviour with the PDP-11 software
@@ -103,7 +156,7 @@ Guide to run operating system images on w11a systems
Under $RETROBASE/tools/simh two setup files are provided with configure
simh to reflect the w11a setup as close as possible:
- setup_w11a_min.scmd
Very close the current w11a state when it runs on an S3BOARD
Very close the current w11a state when it runs on an s3board
- processor: 11/70, no FPP, 1 Mbyte
- periphery: 2 DL11, LP11, RK11, PC11
- setup_w11a_max.scmd
@@ -153,7 +206,8 @@ Guide to run operating system images on w11a systems
- unix-v5_rk: Unix V5 System on RK05
- 211bsd_rk: 2.11BSD system on RK05
- 211bsd_rl: 2.11BSD system on RL02
For further details consult the README_<oskit-name>set.txt file in the
oskit directory.
@@ -186,11 +240,13 @@ Guide to run operating system images on w11a systems
out the W11A and let the author know whether is works as it should.
For convenience the boot scripts are also included ( <kit>.tcl ).
Three oskits are currently provided
Several osskits are currently provided
- rsx11m-31_rk: RSX-11M V3.1 on RK05
- rsx11m-40_rk: RSX-11M V4.0 on RK05
- rt11-40_rk: RT-11 V4.0 on RK05
- rsx11m-31_rk: RSX-11M V3.1 on RK05
- rsx11m-40_rk: RSX-11M V4.0 on RK05
- rt11-40_rk: RT-11 V4.0 on RK05
- rt11-53_rl: RT-11 V5.3 on RL02
- xxdp_rl: XXDP 22 and 25 on RL02
For further details consult the README_<oskit-name>set.txt file in the
oskit directory.

5
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@@ -1,4 +1,7 @@
# $Id: w11a_tb_guide.txt 622 2014-12-28 20:45:26Z mueller $
# $Id: w11a_tb_guide.txt 654 2015-03-01 18:45:38Z mueller $
Note: Only ISE based test benches are currently documented !
The Vivado test environemnt is still in it's infancy !
Guide to running w11a test benches

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rtl/bplib/basys3/basys3_pclk.xdc Normal file
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@@ -0,0 +1,14 @@
# -*- tcl -*-
# $Id: basys3_pclk.xdc 639 2015-01-30 18:12:19Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Primary clocks for Basys3
#
# Revision History:
# Date Rev Version Comment
# 2015-01-25 637 1.0 Initial version
#
create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100]

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@@ -0,0 +1,111 @@
# -*- tcl -*-
# $Id: basys3_pins.xdc 640 2015-02-01 09:56:53Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Pin locks for Basys 3 core functionality
# - USB UART
# - human I/O (switches, buttons, leds, display)
#
# Revision History:
# Date Rev Version Comment
# 2015-01-30 640 1.0 Initial version
#
# config setup --------------------------------------------------------------
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
# clocks -- in bank 34 ------------------------------------------------------
set_property PACKAGE_PIN w5 [get_ports {I_CLK100}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}]
#
# USB UART Interface -- in bank 16 ------------------------------------------
set_property PACKAGE_PIN b18 [get_ports {I_RXD}]
set_property PACKAGE_PIN a18 [get_ports {O_TXD}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}]
set_property DRIVE 12 [get_ports {O_TXD}]
set_property SLEW SLOW [get_ports {O_TXD}]
#
# switches -- in bank 14+34 -------------------------------------------------
set_property PACKAGE_PIN v17 [get_ports {I_SWI[0]}]
set_property PACKAGE_PIN v16 [get_ports {I_SWI[1]}]
set_property PACKAGE_PIN w16 [get_ports {I_SWI[2]}]
set_property PACKAGE_PIN w17 [get_ports {I_SWI[3]}]
set_property PACKAGE_PIN w15 [get_ports {I_SWI[4]}]
set_property PACKAGE_PIN v15 [get_ports {I_SWI[5]}]
set_property PACKAGE_PIN w14 [get_ports {I_SWI[6]}]
set_property PACKAGE_PIN w13 [get_ports {I_SWI[7]}]
set_property PACKAGE_PIN v2 [get_ports {I_SWI[8]}]
set_property PACKAGE_PIN t3 [get_ports {I_SWI[9]}]
set_property PACKAGE_PIN t2 [get_ports {I_SWI[10]}]
set_property PACKAGE_PIN r3 [get_ports {I_SWI[11]}]
set_property PACKAGE_PIN w2 [get_ports {I_SWI[12]}]
set_property PACKAGE_PIN u1 [get_ports {I_SWI[13]}]
set_property PACKAGE_PIN t1 [get_ports {I_SWI[14]}]
set_property PACKAGE_PIN r2 [get_ports {I_SWI[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}]
#
# buttons -- in bank 14 -----------------------------------------------------
# sequence: clockwise(U-R-D-L) - middle - reset
set_property PACKAGE_PIN t18 [get_ports {I_BTN[0]}]
set_property PACKAGE_PIN t17 [get_ports {I_BTN[1]}]
set_property PACKAGE_PIN u17 [get_ports {I_BTN[2]}]
set_property PACKAGE_PIN w19 [get_ports {I_BTN[3]}]
set_property PACKAGE_PIN u18 [get_ports {I_BTN[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}]
#
# LEDs -- in bank 14+34+35 --------------------------------------------------
set_property PACKAGE_PIN u16 [get_ports {O_LED[0]}]
set_property PACKAGE_PIN e19 [get_ports {O_LED[1]}]
set_property PACKAGE_PIN u19 [get_ports {O_LED[2]}]
set_property PACKAGE_PIN v19 [get_ports {O_LED[3]}]
set_property PACKAGE_PIN w18 [get_ports {O_LED[4]}]
set_property PACKAGE_PIN u15 [get_ports {O_LED[5]}]
set_property PACKAGE_PIN u14 [get_ports {O_LED[6]}]
set_property PACKAGE_PIN v14 [get_ports {O_LED[7]}]
set_property PACKAGE_PIN v13 [get_ports {O_LED[8]}]
set_property PACKAGE_PIN v3 [get_ports {O_LED[9]}]
set_property PACKAGE_PIN w3 [get_ports {O_LED[10]}]
set_property PACKAGE_PIN u3 [get_ports {O_LED[11]}]
set_property PACKAGE_PIN p3 [get_ports {O_LED[12]}]
set_property PACKAGE_PIN n3 [get_ports {O_LED[13]}]
set_property PACKAGE_PIN p1 [get_ports {O_LED[14]}]
set_property PACKAGE_PIN l1 [get_ports {O_LED[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}]
set_property DRIVE 12 [get_ports {O_LED[*]}]
set_property SLEW SLOW [get_ports {O_LED[*]}]
#
# 7 segment display -- in bank 34 -------------------------------------------
set_property PACKAGE_PIN u2 [get_ports {O_ANO_N[0]}]
set_property PACKAGE_PIN u4 [get_ports {O_ANO_N[1]}]
set_property PACKAGE_PIN v4 [get_ports {O_ANO_N[2]}]
set_property PACKAGE_PIN w4 [get_ports {O_ANO_N[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_ANO_N[*]}]
set_property DRIVE 12 [get_ports {O_ANO_N[*]}]
set_property SLEW SLOW [get_ports {O_ANO_N[*]}]
#
set_property PACKAGE_PIN w7 [get_ports {O_SEG_N[0]}]
set_property PACKAGE_PIN w6 [get_ports {O_SEG_N[1]}]
set_property PACKAGE_PIN u8 [get_ports {O_SEG_N[2]}]
set_property PACKAGE_PIN v8 [get_ports {O_SEG_N[3]}]
set_property PACKAGE_PIN u5 [get_ports {O_SEG_N[4]}]
set_property PACKAGE_PIN v5 [get_ports {O_SEG_N[5]}]
set_property PACKAGE_PIN u7 [get_ports {O_SEG_N[6]}]
set_property PACKAGE_PIN v7 [get_ports {O_SEG_N[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_SEG_N[*]}]
set_property DRIVE 12 [get_ports {O_SEG_N[*]}]
set_property SLEW SLOW [get_ports {O_SEG_N[*]}]

4
rtl/bplib/basys3/basys3_setup.tcl Normal file
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@@ -0,0 +1,4 @@
# $ Id: $
#
set rvtb_part "xc7a35tcpg236-1"
set rvtb_board "basys3"

46
rtl/bplib/basys3/basys3lib.vhd Normal file
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@@ -0,0 +1,46 @@
-- $Id: basys3lib.vhd 635 2015-01-16 17:37:08Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: basys3ib
-- Description: Basys 3 components
--
-- Dependencies: -
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-15 634 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package basys3lib is
component basys3_aif is -- BASYS 3, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end component;
end package basys3lib;

25
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@@ -0,0 +1,25 @@
# Not meant for direct top level usage. Used with
# tb_basys3_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../basys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_basys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
${basys3_aif := basys3_dummy.vbom}
# design
tb_basys3.vhd
@top:tb_basys3

175
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@@ -0,0 +1,175 @@
-- $Id: tb_basys3.vhd 648 2015-02-20 20:16:21Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_basys3 - sim
-- Description: Test bench for basys3 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_basys3_core
-- serport/serport_uart_rxtx
-- basys3_aif [UUT]
--
-- To test: generic, any basys3_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.basys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_basys3 is
end tb_basys3;
architecture sim of tb_basys3 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv16 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_basys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : basys3_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => O_TXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => I_RXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;

9
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
# design
tb_basys3_core.vhd

71
rtl/bplib/basys3/tb/tb_basys3_core.vhd Normal file
View File

@@ -0,0 +1,71 @@
-- $Id: tb_basys3_core.vhd 648 2015-02-20 20:16:21Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_basys3_core - sim
-- Description: Test bench for basys3 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any basys3 target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4; ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_basys3_core is
port (
I_SWI : out slv16; -- b3 switches
I_BTN : out slv5 -- b3 buttons
);
end tb_basys3_core;
architecture sim of tb_basys3_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;

9
rtl/bplib/bpgen/Makefile
View File

@@ -1,7 +1,8 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-01-24 637 1.1.2 use nexys3 as default XTW_BOARD
# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
@@ -11,9 +12,9 @@ VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ifndef XTW_BOARD
XTW_BOARD=s3board
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -23,7 +24,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

4
rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: bp_rs232_2l4l_iob.vhd 534 2013-09-22 21:37:24Z mueller $
-- $Id: bp_rs232_2l4l_iob.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -21,7 +21,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.26-0.29
-- Tool versions: xst 12.1-14,7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment

4
rtl/bplib/bpgen/bp_rs232_2line_iob.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: bp_rs232_2line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
-- $Id: bp_rs232_2line_iob.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -21,7 +21,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment

4
rtl/bplib/bpgen/bp_rs232_4line_iob.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
-- $Id: bp_rs232_4line_iob.vhd 641 2015-02-01 22:12:15Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -21,7 +21,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment

4
rtl/bplib/bpgen/bp_swibtnled.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: bp_swibtnled.vhd 410 2011-09-18 11:23:09Z mueller $
-- $Id: bp_swibtnled.vhd 637 2015-01-25 18:36:40Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,7 +22,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment

37
rtl/bplib/bpgen/bpgenlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: bpgenlib.vhd 534 2013-09-22 21:37:24Z mueller $
-- $Id: bpgenlib.vhd 637 2015-01-25 18:36:40Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Generic Board/Part components
--
-- Dependencies: -
-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29
-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl
-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob
-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib
-- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus
@@ -124,36 +125,40 @@ component bp_swibtnled is -- generic SWI, BTN and LED handling
);
end component;
component sn_4x7segctl is -- Quad 7 segment display controller
component sn_7segctl is -- 7 segment display controller
generic (
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
DIN : in slv(4*(2**DCWIDTH)-1 downto 0); -- data 16 or 32
DP : in slv((2**DCWIDTH)-1 downto 0); -- decimal points 4 or 8
ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- anodes (act.low) 4 or 8
SEG_N : out slv8 -- segements (act.low)
);
end component;
component sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end component;

32
rtl/bplib/bpgen/bpgenrbuslib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: bpgenrbuslib.vhd 583 2014-08-16 07:40:12Z mueller $
-- $Id: bpgenrbuslib.vhd 637 2015-01-25 18:36:40Z mueller $
--
-- Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Generic Board/Part components using rbus
--
-- Dependencies: -
-- Tool versions: 12.1-14.7; ghdl 0.26-0.31
-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-25 637 1.2 add generics to sn_humanio_rbus
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib)
------------------------------------------------------------------------------
@@ -38,7 +39,7 @@ component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16)));
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -56,32 +57,35 @@ end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16)));
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end component;
component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16)));
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

2
rtl/bplib/bpgen/sn_4x7segctl.vbom → rtl/bplib/bpgen/sn_7segctl.vbom
View File

@@ -2,4 +2,4 @@
../../vlib/slvtypes.vhd
# components
# design
sn_4x7segctl.vhd
sn_7segctl.vhd

79
rtl/bplib/bpgen/sn_4x7segctl.vhd → rtl/bplib/bpgen/sn_7segctl.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
-- $Id: sn_7segctl.vhd 637 2015-01-25 18:36:40Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -12,15 +12,24 @@
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_4x7segctl - syn
-- Description: Quad 7 segment display controller (for s3board and nexys2/3)
-- Module Name: sn_7segctl - syn
-- Description: 7 segment display controller (for s3board,nexys,basys)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-01-24 637 14.7 131013 xc6slx16-2 9 27 0 16 s 3.1 ns DC=3
-- 2015-01-24 637 14.7 131013 xc6slx16-2 8 19 0 9 s 3.1 ns DC=2
-- 2015-01-24 410 14.7 131013 xc6slx16-2 8 19 0 8 s 3.1 ns
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-24 637 1.3 renamed from sn_4x7segctl; add DCWIDTH,
-- allow 4(DC=2) or 8(DC=3) digit display
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
@@ -37,28 +46,28 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
entity sn_4x7segctl is -- Quad 7 segment display controller
entity sn_7segctl is -- 7 segment display controller
generic (
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
DIN : in slv(4*(2**DCWIDTH)-1 downto 0); -- data 16 or 32
DP : in slv((2**DCWIDTH)-1 downto 0); -- decimal points 4 or 8
ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- anodes (act.low) 4 or 8
SEG_N : out slv8 -- segements (act.low)
);
end sn_4x7segctl;
architecture syn of sn_4x7segctl is
end sn_7segctl;
architecture syn of sn_7segctl is
type regs_type is record
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
dcnt : slv(DCWIDTH-1 downto 0); -- digit counter
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(0,CDWIDTH)),
(others=>'0')
slv(to_unsigned(0,CDWIDTH)), -- cdiv
slv(to_unsigned(0,DCWIDTH)) -- dcnt
);
type hex2segtbl_type is array (0 to 15) of slv7;
@@ -84,9 +93,15 @@ architecture syn of sn_4x7segctl is
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CHEX : slv4 := (others=>'0'); -- current hex number
signal CDP : slbit := '0'; -- current decimal point
begin
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity FAILURE;
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity FAILURE;
@@ -101,14 +116,12 @@ begin
end process proc_regs;
proc_next: process (R_REGS, DIN, DP)
proc_next: process (R_REGS, CHEX, CDP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable cano : slv4 := "0000";
variable chex : slv4 := "0000";
variable cdp : slbit := '0';
variable cano : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
begin
r := R_REGS;
@@ -119,17 +132,6 @@ begin
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
chex := "0000";
cdp := '0';
case r.dcnt is
when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
when "10" => chex := DIN(11 downto 8); cdp := DP(2);
when "11" => chex := DIN(15 downto 12); cdp := DP(3);
when others => chex := "----"; cdp := '-';
end case;
-- the logic below ensures that the anode PNP driver transistor is switched
-- off in the last quarter of the digit cycle.This prevents 'cross talk'
-- between digits due to transistor turn off delays.
@@ -141,7 +143,7 @@ begin
-- larger 160 ns and below 320 ns.
-- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz.
cano := "1111";
cano := (others=>'1');
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
@@ -149,8 +151,17 @@ begin
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex))));
SEG_N <= not (CDP & hex2segtbl(to_integer(unsigned(CHEX))));
end process proc_next;
proc_mux: process (R_REGS, DIN, DP)
begin
CDP <= DP(to_integer(unsigned(R_REGS.dcnt)));
CHEX(0) <= DIN(0+4*to_integer(unsigned(R_REGS.dcnt)));
CHEX(1) <= DIN(1+4*to_integer(unsigned(R_REGS.dcnt)));
CHEX(2) <= DIN(2+4*to_integer(unsigned(R_REGS.dcnt)));
CHEX(3) <= DIN(3+4*to_integer(unsigned(R_REGS.dcnt)));
end process proc_mux;
end syn;

2
rtl/bplib/bpgen/sn_humanio.vbom
View File

@@ -5,6 +5,6 @@ bpgenlib.vbom
# components
../../vlib/xlib/iob_reg_o_gen.vbom
bp_swibtnled.vbom
sn_4x7segctl.vbom
sn_7segctl.vbom
# design
sn_humanio.vhd

44
rtl/bplib/bpgen/sn_humanio.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
-- $Id: sn_humanio.vhd 637 2015-01-25 18:36:40Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -13,25 +13,29 @@
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio - syn
-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3
-- Description: BTN,SWI,LED and DSP handling for s3board, nexys, basys
--
-- Dependencies: xlib/iob_reg_o_gen
-- bpgen/bp_swibtnled
-- bpgen/sn_4x7segctl
-- bpgen/sn_7segctl
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-01-24 637 14.7 131013 xc6slx16-2 77 79 0 28 s 3.5 ns (n4)
-- 2015-01-24 637 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns (n2)
-- 2015-01-24 410 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-24 637 1.3 add SWIDTH,LWIDTH,DCWIDTH (for nexys4,basys3)
-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
-- 2011-07-02 387 1.1.2 use bp_swibtnled
@@ -52,34 +56,37 @@ use work.bpgenlib.all;
entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end sn_humanio;
architecture syn of sn_humanio is
signal N_ANO_N : slv4 := (others=>'0');
signal N_ANO_N : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
signal N_SEG_N : slv8 := (others=>'0');
begin
IOB_ANO_N : iob_reg_o_gen
generic map (DWIDTH => 4)
generic map (DWIDTH => 2**DCWIDTH)
port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
IOB_SEG_N : iob_reg_o_gen
@@ -88,9 +95,9 @@ begin
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => 8,
LWIDTH => LWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
@@ -104,8 +111,9 @@ begin
O_LED => O_LED
);
DRV : sn_4x7segctl
DRV : sn_7segctl
generic map (
DCWIDTH => DCWIDTH,
CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
port map (
CLK => CLK,

4
rtl/bplib/bpgen/sn_humanio_demu.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
-- $Id: sn_humanio_demu.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri

4
rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sn_humanio_demu_rbus.vhd 583 2014-08-16 07:40:12Z mueller $
-- $Id: sn_humanio_demu_rbus.vhd 637 2015-01-25 18:36:40Z mueller $
--
-- Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -69,7 +69,7 @@ use work.bpgenlib.all;
entity sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16)));
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

262
rtl/bplib/bpgen/sn_humanio_rbus.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sn_humanio_rbus.vhd 583 2014-08-16 07:40:12Z mueller $
-- $Id: sn_humanio_rbus.vhd 640 2015-02-01 09:56:53Z mueller $
--
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,10 +20,13 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-01-28 639 14.7 131013 xc6slx16-2 253 223 0 97 s 3.6 ns (n4)
-- 2015-01-28 639 14.7 131013 xc6slx16-2 141 120 0 42 s 3.5 ns (n2)
-- 2015-01-25 583 14.7 131013 xc6slx16-2 140 120 0 46 s 3.5 ns
-- 2011-08-14 406 12.1 M53d xc3s1000-4 142 156 0 123 s 5.1 ns
-- 2011-08-07 404 12.1 M53d xc3s1000-4 142 157 0 124 s 5.1 ns
-- 2010-12-29 351 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns
@@ -31,6 +34,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-31 640 2.0 add SWIDTH,LWIDTH,DCWIDTH, change register layout
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus
@@ -43,26 +47,36 @@
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register and BTN access
-- x:08 btn r/w/- r: return hio BTN status
-- w: ored with hio BTN to drive BTN
-- 3 dsp_en r/w/- if 1 display data will be driven by rbus
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
-- 1 led_en r/w/- if 1 LED will be driven by rri
-- 0 swi_en r/w/- if 1 SWI will be driven by rri
--
-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- bbbbbb10 led r/w/- Interface to LED and DSP_DP
-- 15:12 dp r/w/- r: returns DSP_DP status
-- w: will drive display dp's when dp_en=1
-- 7:00 led r/w/- r: returns LED status
-- w: will drive led's when led_en=1
--
-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status
-- w: will drive DSP_DAT when dsp_en=1
-- Addr Bits Name r/w/f Function
-- 000 stat r/-/- Status register
-- 14:12 hdig r/-/- display size as (2**DCWIDTH)-1
-- 11:08 hled r/-/- led size as LWIDTH-1
-- 7:04 hbtn r/-/- button size as BWIDTH-1
-- 3:00 hswi r/-/- switch size as SWIDTH-1
--
-- 001 cntl r/w/- Control register
-- 4 dsp1_en r/w/- if 1 display msb will be driven by rbus
-- 3 dsp0_en r/w/- if 1 display lsb will be driven by rbus
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
-- 1 led_en r/w/- if 1 LED will be driven by rbus
-- 0 swi_en r/w/- if 1 SWI will be driven by rbus
--
-- 010 x:00 btn r/-/f r: return hio BTN status
-- w: will pulse BTN
--
-- 011 x:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- 100 x:00 led r/w/- r: return hio LED status
-- w: will drive LED when led_en=1
--
-- 101 x:00 dp r/w/- r: return hio DSP_DP status
-- w: will drive dp's when dp_en=1
--
-- 110 15:00 dsp0 r/w/- r: return hio DSP_DAT lsb status
-- w: will drive DSP_DAT lsb when dsp_en=1
-- 111 15:00 dsp1 r/w/- r: return hio DSP_DAT msb status
-- w: will drive DSP_DAT msb when dsp_en=1
--
library ieee;
@@ -77,25 +91,28 @@ use work.bpgenlib.all;
entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16)));
RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end sn_humanio_rbus;
@@ -103,68 +120,100 @@ architecture syn of sn_humanio_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv8; -- rbus swi
swi : slv(SWIDTH-1 downto 0); -- rbus swi
btn : slv(BWIDTH-1 downto 0); -- rbus btn
led : slv8; -- rbus led
dsp_dat : slv16; -- rbus dsp_dat
dsp_dp : slv4; -- rbus dsp_dp
ledin : slv8; -- led from design
swieff : slv8; -- effective swi
led : slv(LWIDTH-1 downto 0); -- rbus led
dsp_dat : slv(4*(2**DCWIDTH)-1 downto 0); -- rbus dsp_dat
dsp_dp : slv((2**DCWIDTH)-1 downto 0); -- rbus dsp_dp
ledin : slv(LWIDTH-1 downto 0); -- led from design
swieff : slv(SWIDTH-1 downto 0); -- effective swi
btneff : slv(BWIDTH-1 downto 0); -- effective btn
ledeff : slv8; -- effective led
dpeff : slv4; -- effective dsp_dp
dateff : slv16; -- effective dsp_dat
ledeff : slv(LWIDTH-1 downto 0); -- effective led
dateff : slv(4*(2**DCWIDTH)-1 downto 0); -- effective dsp_dat
dpeff : slv((2**DCWIDTH)-1 downto 0); -- effective dsp_dp
swi_en : slbit; -- enable: swi from rbus
led_en : slbit; -- enable: led from rbus
dsp_en : slbit; -- enable: dsp_dat from rbus
dsp0_en : slbit; -- enable: dsp_dat lsb from rbus
dsp1_en : slbit; -- enable: dsp_dat msb from rbus
dp_en : slbit; -- enable: dsp_dp from rbus
end record regs_type;
constant swizero : slv(SWIDTH-1 downto 0) := (others=>'0');
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant ledzero : slv(LWIDTH-1 downto 0) := (others=>'0');
constant dpzero : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
constant datzero : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- swi
swizero, -- swi
btnzero, -- btn
(others=>'0'), -- led
(others=>'0'), -- dsp_dat
(others=>'0'), -- dsp_dp
(others=>'0'), -- ledin
(others=>'0'), -- swieff
ledzero, -- led
datzero, -- dsp_dat
dpzero, -- dsp_dp
ledzero, -- ledin
swizero, -- swieff
btnzero, -- btneff
(others=>'0'), -- ledeff
(others=>'0'), -- dpeff
(others=>'0'), -- dateff
'0','0','0','0' -- (swi|led|dsp|dp)_en
ledzero, -- ledeff
datzero, -- dateff
dpzero, -- dpeff
'0','0','0','0','0' -- (swi|led|dsp0|dsp1|dp)_en
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
subtype cntl_rbf_btn is integer range BWIDTH+8-1 downto 8;
constant cntl_rbf_dsp_en: integer := 3;
subtype stat_rbf_hdig is integer range 14 downto 12;
subtype stat_rbf_hled is integer range 11 downto 8;
subtype stat_rbf_hbtn is integer range 7 downto 4;
subtype stat_rbf_hswi is integer range 3 downto 0;
constant cntl_rbf_dsp1_en: integer := 4;
constant cntl_rbf_dsp0_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
subtype led_rbf_dp is integer range 15 downto 12;
subtype led_rbf_led is integer range 7 downto 0;
constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/-
constant rbaddr_swi: slv2 := "01"; -- 1 r/w/-
constant rbaddr_led: slv2 := "10"; -- 2 r/w/-
constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/-
constant rbaddr_stat: slv3 := "000"; -- 0 r/-/-
constant rbaddr_cntl: slv3 := "001"; -- 0 r/w/-
constant rbaddr_btn: slv3 := "010"; -- 1 r/-/f
constant rbaddr_swi: slv3 := "011"; -- 1 r/w/-
constant rbaddr_led: slv3 := "100"; -- 2 r/w/-
constant rbaddr_dp: slv3 := "101"; -- 3 r/w/-
constant rbaddr_dsp0: slv3 := "110"; -- 4 r/w/-
constant rbaddr_dsp1: slv3 := "111"; -- 5 r/w/-
signal HIO_SWI : slv8 := (others=>'0');
subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16;
subtype dspdat_lsb is integer range 15 downto 0;
signal HIO_SWI : slv(SWIDTH-1 downto 0) := (others=>'0');
signal HIO_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
signal HIO_LED : slv8 := (others=>'0');
signal HIO_DSP_DAT : slv16 := (others=>'0');
signal HIO_DSP_DP : slv4 := (others=>'0');
signal HIO_LED : slv(LWIDTH-1 downto 0) := (others=>'0');
signal HIO_DSP_DAT : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
signal HIO_DSP_DP : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
begin
assert SWIDTH<=16
report "assert (SWIDTH<=16)"
severity failure;
assert BWIDTH<=8
report "assert (BWIDTH<=8)"
severity failure;
assert LWIDTH<=16
report "assert (LWIDTH<=16)"
severity failure;
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity FAILURE;
HIO : sn_humanio
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => LWIDTH,
DCWIDTH => DCWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
@@ -224,7 +273,7 @@ begin
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
n.rbsel := '1';
end if;
@@ -232,20 +281,35 @@ begin
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_btn) := HIO_BTN;
irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_hdig) := slv(to_unsigned((2**DCWIDTH)-1,3));
irb_dout(stat_rbf_hled) := slv(to_unsigned(LWIDTH-1,4));
irb_dout(stat_rbf_hbtn) := slv(to_unsigned(BWIDTH-1,4));
irb_dout(stat_rbf_hswi) := slv(to_unsigned(SWIDTH-1,4));
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(cntl_rbf_btn);
n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
irb_ack := '0';
end if;
when rbaddr_cntl =>
irb_dout(cntl_rbf_dsp1_en) := r.dsp1_en;
irb_dout(cntl_rbf_dsp0_en) := r.dsp0_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
if RB_MREQ.we = '1' then
n.dsp1_en := RB_MREQ.din(cntl_rbf_dsp1_en);
n.dsp0_en := RB_MREQ.din(cntl_rbf_dsp0_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
end if;
when rbaddr_btn =>
irb_dout(HIO_BTN'range) := HIO_BTN;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(n.btn'range);
end if;
when rbaddr_swi =>
@@ -255,20 +319,30 @@ begin
end if;
when rbaddr_led =>
irb_dout(led_rbf_dp) := HIO_DSP_DP;
irb_dout(led_rbf_led) := r.ledin;
irb_dout(r.ledin'range) := r.ledin;
if RB_MREQ.we = '1' then
n.dsp_dp := RB_MREQ.din(led_rbf_dp);
n.led := RB_MREQ.din(led_rbf_led);
n.led := RB_MREQ.din(n.led'range);
end if;
when rbaddr_dsp =>
irb_dout := HIO_DSP_DAT;
when rbaddr_dp =>
irb_dout(HIO_DSP_DP'range) := HIO_DSP_DP;
if RB_MREQ.we = '1' then
n.dsp_dat := RB_MREQ.din;
n.dsp_dp := RB_MREQ.din(n.dsp_dp'range);
end if;
when rbaddr_dsp0 =>
irb_dout := HIO_DSP_DAT(dspdat_lsb);
if RB_MREQ.we = '1' then
n.dsp_dat(dspdat_lsb) := RB_MREQ.din;
end if;
when others => null;
when rbaddr_dsp1 =>
irb_dout := HIO_DSP_DAT(dspdat_msb);
if RB_MREQ.we = '1' then
n.dsp_dat(dspdat_msb) := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
@@ -293,10 +367,18 @@ begin
n.dpeff := r.dsp_dp;
end if;
if r.dsp_en = '0' then
n.dateff := DSP_DAT;
if r.dsp0_en = '0' then
n.dateff(dspdat_lsb) := DSP_DAT(dspdat_lsb);
else
n.dateff := r.dsp_dat;
n.dateff(dspdat_lsb) := r.dsp_dat(dspdat_lsb);
end if;
if DCWIDTH=3 then
if r.dsp1_en = '0' then
n.dateff(dspdat_msb) := DSP_DAT(dspdat_msb);
else
n.dateff(dspdat_msb) := r.dsp_dat(dspdat_msb);
end if;
end if;
N_REGS <= n;

9
rtl/bplib/fx2lib/Makefile
View File

@@ -1,7 +1,8 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-01-24 637 1.1.2 use nexys3 as default XTW_BOARD
# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-23 293 1.0 Initial version (cloned..)
@@ -10,9 +11,9 @@ VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ifndef XTW_BOARD
XTW_BOARD=nexys2
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -22,7 +23,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

13
rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom
View File

@@ -1,13 +0,0 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
../../vlib/memlib/memlib.vhd
fx2lib.vhd
# components
../../vlib/xlib/iob_reg_o.vbom
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
../../vlib/memlib/fifo_1c_dram.vbom
# design
fx2_2fifoctl_as.vhd

647
rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd
View File

@@ -1,647 +0,0 @@
-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_as - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; async)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_1c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2
-- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2
-- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2
-- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2
-- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic
-- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed)
-- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's
-- 2011-12-25 445 1.2 change pktend handling, now timer based
-- 2011-11-25 433 1.1.1 now numeric_std clean
-- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle
-- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low
-- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port
-- 2011-07-08 390 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_as;
architecture syn of fx2_2fifoctl_as is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_init, -- s_init: init state
s_rdprep, -- s_rdprep: prepare read
s_rdwait, -- s_rdwait: wait for data
s_rdpwl, -- s_rdpwl: read, strobe low
s_rdpwh, -- s_rdpwh: read, strobe high
s_wrprep, -- s_wrprep: prepare write
s_wrpwl, -- s_wrpwl: write, strobe low
s_wrpwh, -- s_wrpwh: write, strobe high
s_peprep, -- s_peprep: prepare pktend
s_pepwl, -- s_pepwl: pktend, strobe low
s_pepwh -- s_pepwh: pktend, strobe high
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
dlycnt : slv4; -- wait delay counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (rx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_init, -- state
petocnt_init, -- petocnt
'0', -- pepend
(others=>'0'), -- cntdly
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
begin
assert RDPWLDELAY<=2**R_REGS.dlycnt'length and
RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and
WRPWLDELAY<=2**R_REGS.dlycnt'length and
WRPWHDELAY<=2**R_REGS.dlycnt'length and
FLAGDELAY<=2**R_REGS.dlycnt'length
report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)"
severity failure;
assert RXAEMPTY_THRES<=2**RXFAWIDTH and
TXAFULL_THRES<=2**TXFAWIDTH
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => CLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => CLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXSIZE
);
TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => TXSIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_USEC,
FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idly_ld : slbit := '0';
variable idly_val : slv(r.dlycnt'range) := (others=>'0');
variable idly_end : slbit := '0';
variable idly_end1 : slbit := '0';
variable iflag_rdok : slbit := '0';
variable iflag_wrok : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
procedure go_rdprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_rxfifo;
nstate := s_rdprep;
end procedure go_rdprep;
procedure go_wrprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_wrprep;
end procedure go_wrprep;
procedure go_peprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_peprep;
end procedure go_peprep;
procedure go_rdpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islrd : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length));
islrd := '1';
nstate := s_rdpwl;
end procedure go_rdpwl;
procedure go_wrpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islwr : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
islwr := '1';
nstate := s_wrpwl;
end procedure go_wrpwl;
procedure go_pepwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ipktend : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
ipktend := '1';
nstate := s_pepwl;
end procedure go_pepwl;
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
imoni := fx2ctl_moni_init;
iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
idly_ld := '0';
idly_val := (others=>'0');
idly_end := '1';
idly_end1 := '0';
if unsigned(r.dlycnt) /= 0 then
idly_end := '0';
end if;
if unsigned(r.dlycnt) = 1 then
idly_end1 := '1';
end if;
case r.state is
when s_init => -- s_init:
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
when s_rdprep => -- s_rdprep: prepare read
if idly_end = '1' then
n.state := s_rdwait;
end if;
when s_rdwait => -- s_rdwait: wait for data
if r.pepend='1' and TXFIFO_VAL='0' then
go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
elsif iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when s_rdpwl => -- s_rdpwl: read, strobe low
idata_cei := '1';
isloe := '1';
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length));
n.state := s_rdpwh;
else
islrd := '1';
n.state := s_rdpwl;
end if;
-- Note: data is sampled and written into rxfifo in 2nd last cycle in the
-- last cycle the rxfifo busy reflects therefore last written byte
-- and safely indicates whether another byte will fit.
when s_rdpwh => -- s_rdpwh: read, strobe high
idata_cei := '1';
isloe := '1';
if idly_end1 = '1' then -- 2nd last cycle
irxfifo_ena := '1'; -- capture rxdata
end if;
if idly_end = '1' then -- last cycle
if iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
else
n.state := s_rdwait;
end if;
end if;
when s_wrprep => -- s_wrprep: prepare write
if idly_end = '1' then
if iflag_wrok = '1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_wrpwl => -- s_wrpwl: write, strobe low
idata_ceo := '1';
idata_oe := '1';
if idly_end = '1' then
idata_ceo := '0';
itxfifo_hold := '0';
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_wrpwh;
else
islwr := '1';
n.state := s_wrpwl;
end if;
when s_wrpwh => -- s_wrpwh: write, strobe high
idata_oe := '1';
if idly_end = '1' then
if iflag_wrok='1' and TXFIFO_VAL='1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_peprep => -- s_peprep: prepare pktend
if idly_end = '1' then
if iflag_wrok = '1' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_pepwl => -- s_pepwl: pktend, strobe low
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_pepwh;
else
ipktend := '1';
n.state := s_pepwl;
end if;
when s_pepwh => -- s_pepwh: pktend, strobe high
if idly_end = '1' then
n.pepend := '0';
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when others => null;
end case;
if idly_ld = '1' then
n.dlycnt := idly_val;
elsif idly_end = '0' then
n.dlycnt := slv(unsigned(r.dlycnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or
r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
else
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
end if;
imoni.fifo_ep4 := r.moni_ep4_sel;
imoni.fifo_ep6 := r.moni_ep6_sel;
imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef);
imoni.flag_ep4_almost := r.moni_ep4_pf;
imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff);
imoni.flag_ep6_almost := r.moni_ep6_pf;
imoni.slrd := islrd;
imoni.slwr := islwr;
imoni.pktend := ipktend;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
MONI <= imoni;
end process proc_next;
proc_almost: process (RXSIZE, TXSIZE)
begin
-- (rx|tx)size is the number of bytes in fifo
-- --> rxsize is number of bytes which can be read
-- --> 2**txfawidth-txsize is is number of bytes which can be written
if unsigned(RXSIZE) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
end syn;

4
rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: fx2_2fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $
-- $Id: fx2_2fifoctl_ic.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -23,7 +23,7 @@
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri

4
rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: fx2_3fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $
-- $Id: fx2_3fifoctl_ic.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -23,7 +23,7 @@
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri

44
rtl/bplib/fx2lib/fx2lib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $
-- $Id: fx2lib.vhd 638 2015-01-25 22:01:38Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,10 +16,11 @@
-- Description: Cypress ez-usb fx2 support
--
-- Dependencies: -
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
-- Tool versions: xst 12.1-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-25 638 1.4 retire fx2_2fifoctl_as
-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
@@ -65,43 +66,6 @@ package fx2lib is
-- -------------------------------------
component fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width

4
rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: fx2_2fifo_core.vhd 469 2013-01-05 12:29:44Z mueller $
-- $Id: fx2_2fifo_core.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,7 +18,7 @@
-- Dependencies: memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-04 469 1.0 Initial version

9
rtl/bplib/fx2rlink/Makefile
View File

@@ -1,7 +1,8 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-01-24 637 1.0.2 use nexys3 as default XTW_BOARD
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2013-04-20 509 1.0 Initial version (cloned..)
#
@@ -9,9 +10,9 @@ VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ifndef XTW_BOARD
XTW_BOARD=nexys2
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -21,7 +22,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

6
rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ioleds_sp1c_fx2.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: ioleds_sp1c_fx2.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,12 +15,12 @@
-- Module Name: ioleds_sp1c_fx2 - syn
-- Description: io activity leds for rlink+serport_1clk+fx2_ic combo
--
-- Dependencies:
-- Dependencies: genlib/led_pulse_stretch
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment

4
rtl/bplib/issi/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -12,7 +12,7 @@ clean : ghdl_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
#
VBOM_all = $(wildcard *.vbom)
#

4
rtl/bplib/issi/is61lv25616al.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: is61lv25616al.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -21,7 +21,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean

4
rtl/bplib/micron/mt45w8mw16b.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: mt45w8mw16b.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -23,7 +23,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.3.2 now numeric_std clean

6
rtl/bplib/nexys2/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys2
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -22,7 +22,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

4
rtl/bplib/nexys2/nexys2lib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: nexys2lib.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: nexys2lib.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,7 +16,7 @@
-- Description: Nexys 2 components
--
-- Dependencies: -
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment

10
rtl/bplib/nexys2/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -17,7 +17,7 @@ EXE_all += tb_nexys2_fusp_cuff_dummy
ifndef XTW_BOARD
XTW_BOARD=nexys2
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

4
rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_core.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_nexys2_core.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core

4
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_nexys2_fusp.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,7 +26,7 @@
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment

4
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: tb_nexys2_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,7 +27,7 @@
-- To test: generic, any nexys2_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment

4
rtl/bplib/nexys3/nexys3lib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: nexys3lib.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,7 +16,7 @@
-- Description: Nexys 3 components
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment

10
rtl/bplib/nexys3/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -11,7 +11,7 @@ EXE_all += tb_nexys3_fusp_cuff_dummy
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -23,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

4
rtl/bplib/nexys3/tb/tb_nexys3_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_core.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_nexys3_core.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)

4
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $
-- $Id: tb_nexys3_fusp.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,7 +26,7 @@
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment

4
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_fusp_cuff.vhd 538 2013-10-06 17:21:25Z mueller $
-- $Id: tb_nexys3_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,7 +27,7 @@
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment

13
rtl/bplib/nexys4/nexys4_pclk.xdc Normal file
View File

@@ -0,0 +1,13 @@
# $Id: nexys4_pclk.xdc 640 2015-02-01 09:56:53Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Primary clocks for Nexys4
#
# Revision History:
# Date Rev Version Comment
# 2015-01-25 639 1.0 Initial version
#
create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100]

132
rtl/bplib/nexys4/nexys4_pins.xdc Normal file
View File

@@ -0,0 +1,132 @@
# -*- tcl -*-
# $Id: nexys4_pins.xdc 643 2015-02-07 17:41:53Z mueller $
#
# Pin locks for Nexys 4 core functionality
# - USB UART
# - human I/O (switches, buttons, leds, display)
#
# Revision History:
# Date Rev Version Comment
# 2015-02-06 643 1.3 factor out cram
# 2015-02-01 641 1.2 separate I_BTNRST_N
# 2015-01-31 640 1.1 fix RTS/CTS
# 2013-10-12 539 1.0 Initial version (converted from ucf)
#
# config setup --------------------------------------------------------------
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
# clocks -- in bank 35 ------------------------------------------------------
set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}]
#
# USB UART Interface -- in bank 35 ------------------------------------------
set_property PACKAGE_PIN c4 [get_ports {I_RXD}]
set_property PACKAGE_PIN d4 [get_ports {O_TXD}]
set_property PACKAGE_PIN d3 [get_ports {O_RTS_N}]
set_property PACKAGE_PIN e5 [get_ports {I_CTS_N}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD O_RTS_N I_CTS_N}]
set_property DRIVE 12 [get_ports {O_TXD O_RTS_N}]
set_property SLEW SLOW [get_ports {O_TXD O_RTS_N}]
#
# switches -- in bank 34 ----------------------------------------------------
set_property PACKAGE_PIN u9 [get_ports {I_SWI[0]}]
set_property PACKAGE_PIN u8 [get_ports {I_SWI[1]}]
set_property PACKAGE_PIN r7 [get_ports {I_SWI[2]}]
set_property PACKAGE_PIN r6 [get_ports {I_SWI[3]}]
set_property PACKAGE_PIN r5 [get_ports {I_SWI[4]}]
set_property PACKAGE_PIN v7 [get_ports {I_SWI[5]}]
set_property PACKAGE_PIN v6 [get_ports {I_SWI[6]}]
set_property PACKAGE_PIN v5 [get_ports {I_SWI[7]}]
set_property PACKAGE_PIN u4 [get_ports {I_SWI[8]}]
set_property PACKAGE_PIN v2 [get_ports {I_SWI[9]}]
set_property PACKAGE_PIN u2 [get_ports {I_SWI[10]}]
set_property PACKAGE_PIN t3 [get_ports {I_SWI[11]}]
set_property PACKAGE_PIN t1 [get_ports {I_SWI[12]}]
set_property PACKAGE_PIN r3 [get_ports {I_SWI[13]}]
set_property PACKAGE_PIN p3 [get_ports {I_SWI[14]}]
set_property PACKAGE_PIN p4 [get_ports {I_SWI[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}]
#
# buttons -- in bank 15+14 --------------------------------------------------
# sequence: clockwise(U-R-D-L) - middle - reset
set_property PACKAGE_PIN f15 [get_ports {I_BTN[0]}]
set_property PACKAGE_PIN r10 [get_ports {I_BTN[1]}]
set_property PACKAGE_PIN v10 [get_ports {I_BTN[2]}]
set_property PACKAGE_PIN t16 [get_ports {I_BTN[3]}]
set_property PACKAGE_PIN e16 [get_ports {I_BTN[4]}]
set_property PACKAGE_PIN c12 [get_ports {I_BTNRST_N}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_BTNRST_N}]
#
# LEDs -- in bank 34 --------------------------------------------------------
set_property PACKAGE_PIN t8 [get_ports {O_LED[0]}]
set_property PACKAGE_PIN v9 [get_ports {O_LED[1]}]
set_property PACKAGE_PIN r8 [get_ports {O_LED[2]}]
set_property PACKAGE_PIN t6 [get_ports {O_LED[3]}]
set_property PACKAGE_PIN t5 [get_ports {O_LED[4]}]
set_property PACKAGE_PIN t4 [get_ports {O_LED[5]}]
set_property PACKAGE_PIN u7 [get_ports {O_LED[6]}]
set_property PACKAGE_PIN u6 [get_ports {O_LED[7]}]
set_property PACKAGE_PIN v4 [get_ports {O_LED[8]}]
set_property PACKAGE_PIN u3 [get_ports {O_LED[9]}]
set_property PACKAGE_PIN v1 [get_ports {O_LED[10]}]
set_property PACKAGE_PIN r1 [get_ports {O_LED[11]}]
set_property PACKAGE_PIN p5 [get_ports {O_LED[12]}]
set_property PACKAGE_PIN u1 [get_ports {O_LED[13]}]
set_property PACKAGE_PIN r2 [get_ports {O_LED[14]}]
set_property PACKAGE_PIN p2 [get_ports {O_LED[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}]
set_property DRIVE 12 [get_ports {O_LED[*]}]
set_property SLEW SLOW [get_ports {O_LED[*]}]
#
# RGB-LEDs -- in bank 15+34+35 ----------------------------------------------
set_property PACKAGE_PIN k5 [get_ports {O_RGBLED0[0]}]
set_property PACKAGE_PIN f13 [get_ports {O_RGBLED0[1]}]
set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[2]}]
set_property PACKAGE_PIN k6 [get_ports {O_RGBLED1[0]}]
set_property PACKAGE_PIN h6 [get_ports {O_RGBLED1[1]}]
set_property PACKAGE_PIN l16 [get_ports {O_RGBLED1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
#
# 7 segment display -- in bank 34 -------------------------------------------
set_property PACKAGE_PIN n6 [get_ports {O_ANO_N[0]}]
set_property PACKAGE_PIN m6 [get_ports {O_ANO_N[1]}]
set_property PACKAGE_PIN m3 [get_ports {O_ANO_N[2]}]
set_property PACKAGE_PIN n5 [get_ports {O_ANO_N[3]}]
set_property PACKAGE_PIN n2 [get_ports {O_ANO_N[4]}]
set_property PACKAGE_PIN n4 [get_ports {O_ANO_N[5]}]
set_property PACKAGE_PIN l1 [get_ports {O_ANO_N[6]}]
set_property PACKAGE_PIN m1 [get_ports {O_ANO_N[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_ANO_N[*]}]
set_property DRIVE 12 [get_ports {O_ANO_N[*]}]
set_property SLEW SLOW [get_ports {O_ANO_N[*]}]
#
set_property PACKAGE_PIN l3 [get_ports {O_SEG_N[0]}]
set_property PACKAGE_PIN n1 [get_ports {O_SEG_N[1]}]
set_property PACKAGE_PIN l5 [get_ports {O_SEG_N[2]}]
set_property PACKAGE_PIN l4 [get_ports {O_SEG_N[3]}]
set_property PACKAGE_PIN k3 [get_ports {O_SEG_N[4]}]
set_property PACKAGE_PIN m2 [get_ports {O_SEG_N[5]}]
set_property PACKAGE_PIN l6 [get_ports {O_SEG_N[6]}]
set_property PACKAGE_PIN m4 [get_ports {O_SEG_N[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_SEG_N[*]}]
set_property DRIVE 12 [get_ports {O_SEG_N[*]}]
set_property SLEW SLOW [get_ports {O_SEG_N[*]}]
#

90
rtl/bplib/nexys4/nexys4_pins_cram.xdc Normal file
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@@ -0,0 +1,90 @@
# -*- tcl -*-
# $Id: nexys4_pins_cram.xdc 643 2015-02-07 17:41:53Z mueller $
#
# Pin locks for Nexys 4 cram
#
# Revision History:
# Date Rev Version Comment
# 2015-02-06 643 1.0 Initial version (derived from nexys4_pins.xdc)
#
# CRAM -- in bank 14+15 -----------------------------------------------------
set_property PACKAGE_PIN l18 [get_ports {O_MEM_CE_N}]
set_property PACKAGE_PIN r11 [get_ports {O_MEM_WE_N}]
set_property PACKAGE_PIN h14 [get_ports {O_MEM_OE_N}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}]
set_property DRIVE 12 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}]
set_property SLEW FAST [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}]
#
set_property PACKAGE_PIN j15 [get_ports {O_MEM_BE_N[0]}]
set_property PACKAGE_PIN j13 [get_ports {O_MEM_BE_N[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_BE_N[*]}]
set_property DRIVE 12 [get_ports {O_MEM_BE_N[*]}]
set_property SLEW FAST [get_ports {O_MEM_BE_N[*]}]
#
set_property PACKAGE_PIN t13 [get_ports {O_MEM_ADV_N}]
set_property PACKAGE_PIN t15 [get_ports {O_MEM_CLK}]
set_property PACKAGE_PIN j14 [get_ports {O_MEM_CRE}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}]
set_property DRIVE 12 [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}]
set_property SLEW FAST [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}]
#
set_property PACKAGE_PIN t14 [get_ports {I_MEM_WAIT}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_MEM_WAIT}]
#
set_property PACKAGE_PIN j18 [get_ports {O_MEM_ADDR[0]}]
set_property PACKAGE_PIN h17 [get_ports {O_MEM_ADDR[1]}]
set_property PACKAGE_PIN h15 [get_ports {O_MEM_ADDR[2]}]
set_property PACKAGE_PIN j17 [get_ports {O_MEM_ADDR[3]}]
set_property PACKAGE_PIN h16 [get_ports {O_MEM_ADDR[4]}]
set_property PACKAGE_PIN k15 [get_ports {O_MEM_ADDR[5]}]
set_property PACKAGE_PIN k13 [get_ports {O_MEM_ADDR[6]}]
set_property PACKAGE_PIN n15 [get_ports {O_MEM_ADDR[7]}]
set_property PACKAGE_PIN v16 [get_ports {O_MEM_ADDR[8]}]
set_property PACKAGE_PIN u14 [get_ports {O_MEM_ADDR[9]}]
set_property PACKAGE_PIN v14 [get_ports {O_MEM_ADDR[10]}]
set_property PACKAGE_PIN v12 [get_ports {O_MEM_ADDR[11]}]
set_property PACKAGE_PIN p14 [get_ports {O_MEM_ADDR[12]}]
set_property PACKAGE_PIN u16 [get_ports {O_MEM_ADDR[13]}]
set_property PACKAGE_PIN r15 [get_ports {O_MEM_ADDR[14]}]
set_property PACKAGE_PIN n14 [get_ports {O_MEM_ADDR[15]}]
set_property PACKAGE_PIN n16 [get_ports {O_MEM_ADDR[16]}]
set_property PACKAGE_PIN m13 [get_ports {O_MEM_ADDR[17]}]
set_property PACKAGE_PIN v17 [get_ports {O_MEM_ADDR[18]}]
set_property PACKAGE_PIN u17 [get_ports {O_MEM_ADDR[19]}]
set_property PACKAGE_PIN t10 [get_ports {O_MEM_ADDR[20]}]
set_property PACKAGE_PIN m16 [get_ports {O_MEM_ADDR[21]}]
set_property PACKAGE_PIN u13 [get_ports {O_MEM_ADDR[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_ADDR[*]}]
set_property DRIVE 8 [get_ports {O_MEM_ADDR[*]}]
set_property SLEW FAST [get_ports {O_MEM_ADDR[*]}]
#
set_property PACKAGE_PIN r12 [get_ports {IO_MEM_DATA[0]}]
set_property PACKAGE_PIN t11 [get_ports {IO_MEM_DATA[1]}]
set_property PACKAGE_PIN u12 [get_ports {IO_MEM_DATA[2]}]
set_property PACKAGE_PIN r13 [get_ports {IO_MEM_DATA[3]}]
set_property PACKAGE_PIN u18 [get_ports {IO_MEM_DATA[4]}]
set_property PACKAGE_PIN r17 [get_ports {IO_MEM_DATA[5]}]
set_property PACKAGE_PIN t18 [get_ports {IO_MEM_DATA[6]}]
set_property PACKAGE_PIN r18 [get_ports {IO_MEM_DATA[7]}]
set_property PACKAGE_PIN f18 [get_ports {IO_MEM_DATA[8]}]
set_property PACKAGE_PIN g18 [get_ports {IO_MEM_DATA[9]}]
set_property PACKAGE_PIN g17 [get_ports {IO_MEM_DATA[10]}]
set_property PACKAGE_PIN m18 [get_ports {IO_MEM_DATA[11]}]
set_property PACKAGE_PIN m17 [get_ports {IO_MEM_DATA[12]}]
set_property PACKAGE_PIN p18 [get_ports {IO_MEM_DATA[13]}]
set_property PACKAGE_PIN n17 [get_ports {IO_MEM_DATA[14]}]
set_property PACKAGE_PIN p17 [get_ports {IO_MEM_DATA[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_MEM_DATA[*]}]
set_property DRIVE 8 [get_ports {IO_MEM_DATA[*]}]
set_property SLEW SLOW [get_ports {IO_MEM_DATA[*]}]
set_property KEEPER true [get_ports {IO_MEM_DATA[*]}]
#

4
rtl/bplib/nexys4/nexys4_setup.tcl Normal file
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# $ Id: $
#
set rvtb_part "xc7a100tcsg324-1"
set rvtb_board "nexys4"

81
rtl/bplib/nexys4/nexys4lib.vhd Normal file
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-- $Id: nexys4lib.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: nexys4lib
-- Description: Nexys 4 components
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.2 factor out memory, add nexys4_cram_aif
-- 2015-02-01 641 1.1 drop nexys4_fusp_aif; separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nexys4lib is
component nexys4_aif is -- NEXYS 4, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end component;
component nexys4_cram_aif is -- NEXYS 4, abstract iface, base+cram
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
end package nexys4lib;

5
rtl/bplib/nexys4/tb/.cvsignore Normal file
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tb_nexys4_dummy
tb_nexys4_cram_dummy
nexys4_dummy.ucf
nexys4_cram_dummy.ucf
*.dep_ucf_cpp

39
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# $Id: Makefile.ise 648 2015-02-20 20:16:21Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-02-06 643 1.2 add nexys4_cram_aif
# 2015-02-01 641 1.1 drop nexys4_fusp_aif
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2013-09-21 534 1.0 Initial version
#
EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy
#
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
endif
#

25
rtl/bplib/nexys4/tb/tb_nexys4.vbom Normal file
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# Not meant for direct top level usage. Used with
# tb_nexys4_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_nexys4_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
${nexys4_aif := nexys4_dummy.vbom}
# design
tb_nexys4.vhd
@top:tb_nexys4

189
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-- $Id: tb_nexys4.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4 - sim
-- Description: Test bench for nexys4 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_nexys4_core
-- serport/serport_uart_rxtx
-- nexys4_aif [UUT]
--
-- To test: generic, any nexys4_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4 is
end tb_nexys4;
architecture sim of tb_nexys4 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => O_TXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => I_RXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;

9
rtl/bplib/nexys4/tb/tb_nexys4_core.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
# design
tb_nexys4_core.vhd

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-- $Id: tb_nexys4_core.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_core - sim
-- Description: Test bench for nexys4 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any nexys4 target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_nexys4_core is
port (
I_SWI : out slv16; -- n4 switches
I_BTN : out slv5; -- n4 buttons
I_BTNRST_N : out slbit -- n4 reset button
);
end tb_nexys4_core;
architecture sim of tb_nexys4_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
signal R_BTNRST : slbit := '0';
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
R_BTNRST <= to_x01(SB_DATA(5));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
I_BTNRST_N <= not R_BTNRST;
end sim;

26
rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom Normal file
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# Not meant for direct top level usage. Used with
# tb_nexys4_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_nexys4_core.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
${nexys4_cram_aif := nexys4_cram_dummy.vbom}
# design
tb_nexys4_cram.vhd
@top:tb_nexys4_cram

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-- $Id: tb_nexys4_cram.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_cram - sim
-- Description: Test bench for nexys4 (base+cram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_nexys4_core
-- serport/serport_uart_rxtx
-- nexys4_cram_aif [UUT]
-- vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys4_cram_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4_cram is
end tb_nexys4_cram;
architecture sim of tb_nexys4_cram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4_cram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => O_TXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => I_RXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;

9
rtl/bplib/nxcramlib/Makefile
View File

@@ -1,7 +1,8 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-01-24 637 1.0.2 use nexys3 as default XTW_BOARD
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2011-11-26 433 1.0 Initial version (cloned..)
#
@@ -9,9 +10,9 @@ VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ifndef XTW_BOARD
XTW_BOARD=nexys2
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -21,7 +22,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

4
rtl/bplib/nxcramlib/nx_cram_dummy.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: nx_cram_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: nx_cram_dummy.vhd 641 2015-02-01 22:12:15Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from n2_cram_dummy

6
rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: nx_cram_memctl_as.vhd 563 2014-06-22 15:49:09Z mueller $
-- $Id: nx_cram_memctl_as.vhd 644 2015-02-08 22:56:54Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -21,7 +21,7 @@
-- Test bench: tb/tb_nx_cram_memctl_as
-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -182,7 +182,7 @@ architecture syn of nx_cram_memctl_as is
end record regs_type;
constant regs_init : regs_type := (
s_idle, --
s_idle, -- state
'0', -- ackr
'0', -- addr0
"00", -- be2nd

4
rtl/bplib/nxcramlib/nxcramlib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: nxcramlib.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: nxcramlib.vhd 641 2015-02-01 22:12:15Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,7 +16,7 @@
-- Description: Nexys 2/3 CRAM drivers
--
-- Dependencies: -
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment

13
rtl/bplib/nxcramlib/tb/Makefile
View File

@@ -1,16 +1,17 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-01-24 637 1.0.2 use nexys3 as default XTW_BOARD
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2011-11-26 433 1.0 Initial version (cloned)
#
EXE_all = tb_nx_cram_memctl_as
#
ifndef XTW_BOARD
XTW_BOARD=nexys2
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -22,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

4
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
-- $Id: tb_nx_cram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -23,7 +23,7 @@
-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as)
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt

4
rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tbd_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tbd_nx_cram_memctl_as.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,7 +27,7 @@
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 122 0 107 t 11.4
-- 2010-05-30 297 11.4 L68 xc3s1200e-4 91 99 0 95 t 13.1
--
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as

6
rtl/bplib/s3board/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=s3board
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -23,7 +23,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

4
rtl/bplib/s3board/s3_sram_dummy.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
-- $Id: s3_sram_dummy.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-04-17 278 1.0.2 renamed from sram_dummy

6
rtl/bplib/s3board/s3_sram_memctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -21,7 +21,7 @@
-- Test bench: tb/tb_s3_sram_memctl
-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -124,7 +124,7 @@ architecture syn of s3_sram_memctl is
end record regs_type;
constant regs_init : regs_type := (
s_idle,
s_idle, -- state
'0' -- ackr
);

4
rtl/bplib/s3board/s3boardlib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: s3boardlib.vhd 426 2011-11-18 18:14:08Z mueller $
-- $Id: s3boardlib.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,7 +16,7 @@
-- Description: S3BOARD components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib

10
rtl/bplib/s3board/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -17,7 +17,7 @@ EXE_all += tb_s3_sram_memctl
ifndef XTW_BOARD
XTW_BOARD=s3board
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

4
rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: s3board_fusp_dummy.vhd 336 2010-11-06 18:28:27Z mueller $
-- $Id: s3board_fusp_dummy.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,7 +18,7 @@
-- Dependencies: -
-- To test: tb_s3board_fusp
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50

4
rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3_sram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
-- $Id: tb_s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,7 +28,7 @@
-- 2007-12-16 101 - 0.26 - - c:ok
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt

4
rtl/bplib/s3board/tb/tb_s3board_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3board_core.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_s3board_core.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean

4
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3board_fusp.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_s3board_fusp.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -25,7 +25,7 @@
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface

6
rtl/ibus/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -23,7 +23,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

4
rtl/ibus/ib_intmap.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ib_intmap.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: ib_intmap.vhd 641 2015-02-01 22:12:15Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean

Some files were not shown because too many files have changed in this diff Show More