wfjm.w11

mirror of https://github.com/wfjm/w11.git synced 2026-02-28 09:37:47 +00:00

Files

wfjm 67437bf140 minor cleanups; update vmfset and imfset

- Makefile: drop ISE targets except for w11a
- rtl/sys_gen/**/*.*mfset: accomodate recent changes
- rtl/w11a
  - pdp11_dpath.vhd: remove PCOUT port
  - pdp11_sequencer.vhd: remove PC port

2022-12-27 13:32:12 +01:00

arty

add vlib/xlib/bufg_unisim, encapulate unisim BUFG

2022-07-06 09:34:15 +02:00

cmoda7

minor cleanups; update vmfset and imfset

2022-12-27 13:32:12 +01:00

nexys2

SPDX: rtl/*/*.vhd

2019-07-12 19:01:49 +02:00

nexys3

SPDX: rtl/*/*.vhd

2019-07-12 19:01:49 +02:00

nexys4

build flow now Vivado 2022.1 ready [skip ci]

2022-05-28 08:47:11 +02:00

nexys4d

minor cleanups; update vmfset and imfset

2022-12-27 13:32:12 +01:00

s3board

SPDX: rtl/*/*.vhd

2019-07-12 19:01:49 +02:00

README.md

docu updates [skip ci]

2019-08-11 09:50:44 +02:00

tbrun.yml

cleanup tbrun setup, drop nexys4 and add nexys4d

2022-04-30 08:22:27 +02:00

tst_sram.vbom

fix dangling ${sys_conf}; tmuconv update [skip ci]

2022-07-19 07:53:26 +02:00

tst_sram.vhd

SPDX: rtl/*/*.vhd

2019-07-12 19:01:49 +02:00

README.md

This directory sub-tree contains memory tester systems and is organized in

Directory	Content
arty	design for Digilent Arty A7-35
cmoda7	design for Digilent Cmod A7-35
nexys2	design for Digilent Nexys2
nexys3	design for Digilent Nexys3
nexys4	design for Digilent Nexys4 (old CRAM version)
nexys4d	design for Digilent Nexys A7-100
s3board	design for Digilent S3BOARD