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123 lines
4.2 KiB
VHDL
123 lines
4.2 KiB
VHDL
-- $Id: gray_cnt_5.vhd 1371 2023-02-10 11:14:03Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: gray_cnt_5 - syn
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-- Description: 5 bit Gray code counter (ROM based)
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.1-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
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-- Revision History:
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-- Date Rev Version Comment
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-- 2017-01-07 840 1.1 disable fsm recognition in vivado
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-- 2007-12-26 106 1.0 Initial version
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--
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-- Some synthesis results (after synthesis step):
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-- - 2023-02-10 viv 2022.1 for xc7a100tcsg324-1:
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-- LUT Flop
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-- 5 5
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-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
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-- LUT Flop clock(xst est.)
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-- 9 5 302MHz/ 3.31ns
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity gray_cnt_5 is -- 5 bit gray code counter (ROM based)
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv5 -- data out
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);
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end entity gray_cnt_5;
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architecture syn of gray_cnt_5 is
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signal R_DATA : slv5 := (others=>'0');
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signal N_DATA : slv5 := (others=>'0');
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-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm
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-- is inferred, using 'Johnson' encoding. DATA will be deduced
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-- in a combinatorial logic, and will thus have very likely some
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-- glitches at the clock transitions, rendering the whole Gray
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-- coding useless.
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attribute fsm_extract : string;
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attribute fsm_extract of R_DATA : signal is "no";
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attribute rom_style : string;
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attribute rom_style of N_DATA : signal is "distributed";
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-- Note: vivado started with -fsm_extraction one_hot didn't fsm recognize
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-- this code up to 2016.2. With 2016.3 and later it is converted into a
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-- 31 state one-hot fsm, unless explicitely suppressed
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attribute fsm_encoding : string;
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attribute fsm_encoding of R_DATA : signal is "none";
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_DATA <= (others=>'0');
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elsif CE = '1' then
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R_DATA <= N_DATA;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_DATA)
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begin
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N_DATA <= (others=>'0');
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case R_DATA is
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when "00000" => N_DATA <= "00001"; -- 0
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when "00001" => N_DATA <= "00011"; -- 1
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when "00011" => N_DATA <= "00010"; -- 2
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when "00010" => N_DATA <= "00110"; -- 3
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when "00110" => N_DATA <= "00111"; -- 4
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when "00111" => N_DATA <= "00101"; -- 5
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when "00101" => N_DATA <= "00100"; -- 6
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when "00100" => N_DATA <= "01100"; -- 7
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when "01100" => N_DATA <= "01101"; -- 8
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when "01101" => N_DATA <= "01111"; -- 9
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when "01111" => N_DATA <= "01110"; -- 10
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when "01110" => N_DATA <= "01010"; -- 11
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when "01010" => N_DATA <= "01011"; -- 12
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when "01011" => N_DATA <= "01001"; -- 13
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when "01001" => N_DATA <= "01000"; -- 14
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when "01000" => N_DATA <= "11000"; -- 15
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when "11000" => N_DATA <= "11001"; -- 16
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when "11001" => N_DATA <= "11011"; -- 17
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when "11011" => N_DATA <= "11010"; -- 18
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when "11010" => N_DATA <= "11110"; -- 19
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when "11110" => N_DATA <= "11111"; -- 20
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when "11111" => N_DATA <= "11101"; -- 21
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when "11101" => N_DATA <= "11100"; -- 22
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when "11100" => N_DATA <= "10100"; -- 23
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when "10100" => N_DATA <= "10101"; -- 24
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when "10101" => N_DATA <= "10111"; -- 25
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when "10111" => N_DATA <= "10110"; -- 26
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when "10110" => N_DATA <= "10010"; -- 27
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when "10010" => N_DATA <= "10011"; -- 28
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when "10011" => N_DATA <= "10001"; -- 29
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when "10001" => N_DATA <= "10000"; -- 30
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when "10000" => N_DATA <= "00000"; -- 31
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when others => null;
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end case;
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end process proc_next;
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DATA <= R_DATA;
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end syn;
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