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14362b2a56
- arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model
6 lines
68 B
Plaintext
6 lines
68 B
Plaintext
# libs
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../slvtypes.vhd
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@lib:unisim
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# design
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s7_cmt_sfs_2_unisim.vhd
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