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56 lines
2.6 KiB
Markdown
56 lines
2.6 KiB
Markdown
## divtst: a program testing DIV instruction response
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The `divtst` program tests the `DIV` instruction with a set of test
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cases and checks whether the response agrees with the expected values.
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The program is available in two versions
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- for BSD Unix systems, written in C and assembler, see directory [bsd](bsd)
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- for RSX systems, written in MACRO-11 assembler, see directory [rsx](rsx)
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Some results for different systems is available in directory [data](data).
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The `divtst` program read the test cases from a file with the high and low part
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of dividend and the divisor followed by _expected_ condition codes, quotient,
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and remainder. All in octal like
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```
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; ddh ddl dr : nzvc q r # comments
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000000 000000 000003 : 0100 000000 000000 # 0/ 3: 0, 0
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000000 000004 000003 : 0000 000001 000001 # 4/ 3: 1, 1
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025253 052525 125252 : 1000 100000 052525 # 715871573/-21846:-32768, 21845
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000000 000000 000000 : 0111 000000 000000 # 0/ 0: 0, 0
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025253 052527 125252 : 1010 025253 052527 # 715871575/-21846: 10923, 21847
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```
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The comment gives dividend, divisor, quotient, and remainder in decimal for
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easier understanding, but is not interpreted by the program.
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The output has the same format and contains _found_ condition codes quotient
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and remainder. If the found response differs from the expected values
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error indicators are added
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```
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CBAD for C mismatch
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VBAD for V mismatch
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ZBAD for Z mismatch (only checked if V=0)
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NBAD for N mismatch (only checked if V=0)
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QBAD for quotient mismatch (only checked if V=0)
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RBAD for remainder mismatch (only checked if V=0)
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```
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Note that the N and Z condition codes are _unspecified_ for the `DIV`
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instruction after a zero divide or overflow abort, which both set V=1.
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The `w11` sets N=0 Z=1 for zero divide and Z=0 and N to the expected sign
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of the result for an overflow. Same does SimH. The expected condition codes
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in the file [tstall.dat](tstall.dat) are set like this for V=1 cases,
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but not checked.
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The state of the two result registers is also not specified when V=1 is set.
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In some CPUs and some cases the registers preserve the original state, in other
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cases, they are written. This is flagged with two markers
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```
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R0MOD for R0 changed when V=1 seen (quotient result register)
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R1MOD for R1 changed when V=1 seen (remainder result register)
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```
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Notes:
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- markers do not indicate an error, they just flag how `DIV` behaves in
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these unspecified cases.
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- the test `DIV` instruction uses `r0` as destination, quotient and remainder
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go to `r0` and `r1`. Better naming for the flags might have been `RQMOD`
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and `RRMOD`.
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