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25 lines
1.2 KiB
Markdown
25 lines
1.2 KiB
Markdown
## Known differences between w11a and KB11-C (11/70)
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### The 'instruction completed flag' in `MMR0` is not implemented
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All PDP-11 processors with a fully functional MMU (11/45, 11/70, 11/44, and J11)
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support the re-execution of an instruction after an MMU abort.
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`MMR2` holds the virtual address of aborted instruction and `MMR1` holds
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information about register changes. This can be used by a handler to roll back
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the register changes and restart the instruction. This can be used to
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implement demand paging or dynamic extension of stack segments.
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The 11/70 and 11/45 are the only PDP-11 processors that also support the
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recovery of an MMU abort of a stack push during trap or interrupt processing.
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To distinguish between an instruction and a trap processing abort the
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`MMR1` has a bit called `instruction completed`. It is will be set to 0
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whenever an instruction is aborted and is 1 after a trap service flow is
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aborted. The `MMR2` contains the vector address in the latter case.
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Only the 11/70 and the 11/45 support this. No OS uses this.
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And it's very difficult to construct a practical use case.
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The w11a doesn't support the 'instruction completed' bit in `MMR1`. It is
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always 0. And `MMR2` holds always the virtual address of the last instruction.
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