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32 lines
1.5 KiB
Markdown
32 lines
1.5 KiB
Markdown
## divtst: data collection
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`divstst` has been run on real PDP-11 CPUs as well as on simulated CPUs
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with the [SimH](http://simh.trailing-edge.com/) and the
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[e11](http://www.dbit.com/) simulator.
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The results are available in
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| Case | sim | CPU | Comment |
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| --------- | --- | --- | ------- |
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| [2014-08-22_1170_btq](2014-08-22_1170_btq.log) | real | 11/70 | from Johnny Billquist, node magica |
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| [2014-08-22_1193_btq](2014-08-22_1170_btq.log) | real | 11/93 (J11) | from Johnny Billquist, node pontus |
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| [2014-08-22_e11_1174_btq](2014-08-22_e11_1174_btq.log) | e11 | 11/74 | from Johnny Billquist, node mim |
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| [2014-08-22_simh_1194_btq](2014-08-22_simh_1194_btq.log) | SimH | 11/94 (J11) | from Johnny Billquist, node jocke |
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| [2022-08-11_w11a_wfjm](2022-08-11_w11a_wfjm.log) | | w11a | from wfjm |
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The file name encodes the approximate date of data taking (relevant for
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simulators which indeed change over time), the sim/CPU case, and the source
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of data.
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### Some findings
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The N and Z condition codes and the registers are _unspecified_ after an
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overflow abort of the `DIV` instruction. The only thing guaranteed is
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that V=1 and C=0. The seen responses for the _unspecified_ parts
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are indeed different, a good example is
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```
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ddh ddl dr : nzvc q r remarks
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177777 100000 177777 : 0110 000000 100000 real 11/70: Z=1, R0MOD
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177777 100000 177777 : 0010 177777 100000 real 11/93: r0,r1 unchanged
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177777 100000 177777 : 0010 100000 000000 e11 11/74: R0MOD R1MOD
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177777 100000 177777 : 0010 177777 100000 w11a: r0,r1 unchanged
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```
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