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31 lines
1.5 KiB
Markdown
31 lines
1.5 KiB
Markdown
## Known differences between SimH, 11/70, and w11a
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### SimH: The 'instruction completed flag' in `MMR0` is not implemented
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All PDP-11 processors with a fully functional MMU (11/45, 11/70, 11/44, and J11)
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support the re-execution of an instruction after an MMU abort.
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`MMR2` holds the virtual address of aborted instruction and `MMR1` holds
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information about register changes. This can be used by a handler to roll back
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the register changes and restart the instruction. This can be used to
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implement demand paging or dynamic extension of stack segments.
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The 11/70 and 11/45 are the only PDP-11 processors that also support the
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recovery of an MMU abort of a stack push during trap or interrupt processing.
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To distinguish between an instruction and a trap processing abort the
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`MMR1` has a bit called `instruction completed`. It is will be set to 0
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whenever an instruction is aborted and is 1 after a trap service flow is
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aborted. The `MMR2` contains the vector address in the latter case.
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SimH does not support the `MMR0` `instruction completed` flag and the
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associated `MMR2` behavior.
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xxdp program `ekbee1` test 067 verifies this behavior and is skipped
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(see [patch](../tools/xxdp/ekbee1_patch_1170.scmd)).
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w11 supports `instruction completed` with some minor implementation differences,
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see [w11 known difference](w11a_diff_70_instruction_complete.md).
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This is verified in a [tcode](../tools/tcode/README.md), the tests are skipped
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when executed on SimH
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(see [cpu_mmu.mac](../tools/tcode/cpu_mmu.mac) test C2.6 and D2.1).
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Tested with SimH V3.12-3.
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