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- rtl/w11a - pdp11.vhd: vm_stat_type: add err_ser - pdp11_sequencer.vhd: BUGFIX: handle CPUERR.rsv correctly - pdp11_vmbox.vhd: use err_ser to indicate fatal stack error - tools/tcode/cpu_details.mac: update A2.7-10
38 lines
2.3 KiB
Markdown
38 lines
2.3 KiB
Markdown
# Known differences between SimH, 11/70, and w11a
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The SimH simulator focuses on the behavior that is relevant to the normal
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operation of operating systems and user code. Model differences that are
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operation relevant, e.g. in probe routines or model-dependent kernel routines,
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are handled correctly epending on the `set cpu` configuration.
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However, many model variations that do not effect normal operation are not
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modeled for performance reasons. In these cases, the J11 behavior is often used
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for all PDP-11 models, and also when `set cpu 11/70` is configured.
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Test codes are sometimes sensitive to those details, so the most relevant
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ones are listed here:
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- instruction behavior
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- [SimH: `SPL` doesn't have 11/70 behavior](simh_diff_spl.md)
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- [SimH: State of N and Z and registers after a `DIV` abort with `V=1`](simh_diff_div_after_v1.md)
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- [SimH: `JSR SP` pushes modified `SP` value](simh_diff_jsr_sp.md)
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- stack limit and stack error behavior
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- [SimH: stack limit check and addressing modes](simh_diff_stklim_amode.md)
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- [SimH: stack limit check and vector push aborts](simh_diff_stklim_vpush.md)
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- [SimH: Red stack zone PSW protection](simh_diff_red_psw.md)
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- [SimH: `CPUERR.rsv` has J11 behavior](simh_diff_cpuerr_rsv.md)
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- [SimH: No unconditional instruction fetch after stack error abort](simh_diff_ser_forced_fetch.md)
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- instruction abort handling
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- [SimH: condition codes are not always unchanged after an abort](simh_diff_cc_and_aborts.md)
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- service order and trap handling
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- [SimH: trap and interrupt service order has J11 behavior](simh_diff_service-order.md)
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- [SimH: traced `WAIT` has J11 behavior](simh_diff_traced-wait.md)
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- [SimH: traced `RTI`/`RTT` that clears tbit does trap](simh_diff_traced-rti-rtt.md)
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- [SimH: vector flow that sets tbit does not trap](simh_diff_traced-vector.md)
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- memory management behavior
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- [SimH: `MMR1` recording has J11 behavior](simh_diff_mmr1.md)
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- [SimH: MMU traps not suppressed when MMU register accessed](simh_diff_mmu_trap_suppression.md)
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- [SimH: The 'instruction completed flag' in `MMR0` is not implemented](simh_diff_instruction_complete.md)
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- [SimH: MMU aborts have priority over NXM aborts](simh_diff_mmu_nxm_prio.md)
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- not implemented 11/70 features
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- [SimH: 18-bit UNIBUS address space not mapped](simh_diff_unibus_mapping.md)
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- [SimH: MMU maintenance mode not implemented](simh_diff_mmu_no_maint.md)
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