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102 lines
3.0 KiB
VHDL
102 lines
3.0 KiB
VHDL
-- $Id: crc8.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: crc8 - syn
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-- Description: 8bit CRC generator, use CRC-8-SAE J1850 polynomial.
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-- Based on CRC-8-SAE J1850 polynomial:
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-- x^8 + x^4 + x^3 + x^2 + 1 (0x1d)
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-- It is irreducible, and can be implemented with <= 54 xor's
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--
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-- Notes: # XST synthesis for a Spartan-3 gives:
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-- 1-bit xor2 : 11
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-- 1-bit xor4 : 5
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-- 1-bit xor5 : 1
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-- Number of 4 input LUTs: 20
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-- # Synthesis with crc8_update_tbl gives a lut-rom based table
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-- design. Even though a 256x8 bit ROM is behind, the optimizer
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-- gets it into 12 slices with 22 4 input LUTs, thus only
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-- little larger than with xor's.
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.comlib.all;
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entity crc8 is -- crc-8 generator, checker
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generic (
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INIT: slv8 := "00000000"); -- initial state of crc register
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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ENA : in slbit; -- update enable
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DI : in slv8; -- input data
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CRC : out slv8 -- crc code
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);
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end crc8;
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architecture syn of crc8 is
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signal R_CRC : slv8 := INIT; -- state registers
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signal N_CRC : slv8 := INIT; -- next value state regs
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begin
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proc_regs: process (CLK)
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begin
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if CLK'event and CLK='1' then
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if RESET = '1' then
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R_CRC <= INIT;
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else
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R_CRC <= N_CRC;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_CRC, DI, ENA)
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variable r : slv8 := INIT;
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variable n : slv8 := INIT;
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begin
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r := R_CRC;
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n := R_CRC;
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if ENA = '1' then
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crc8_update(n, DI);
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end if;
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N_CRC <= n;
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CRC <= R_CRC;
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end process proc_next;
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end syn;
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