mirror of
https://github.com/wfjm/w11.git
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cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
211 lines
9.1 KiB
C
211 lines
9.1 KiB
C
/* $Id: usb_fifo_init.c 450 2012-01-05 23:21:41Z mueller $ */
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/*
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* Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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* Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
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* The data fifo treatment is partially inspired by work of Marco Oster
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* done at ZITI, Heidelberg in 2010.
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*
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* - original copyright and licence disclaimer (of usb_jtag_init) -------------
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* - Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter
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* - Copyright (C) 2005..2007 Kolja Waschk, ixo.de
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* - This code is part of usbjtag. usbjtag is free software;
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*-----------------------------------------------------------------------------
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*
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* This program is free software; you may redistribute and/or modify it under
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* the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 2, or at your option any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for complete details.
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*
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*-----------------------------------------------------------------------------
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*
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* USB FIFO setup
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*
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* Revision History:
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*
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* Date Rev Version Comment
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* 2012-01-04 450 1.5 new FLAGS layout (D=8-FF,C=4-EF,B=6-FF,A=indexed)
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* 2012-01-02 448 1.4 add support for sync fifo w/ int. clock (_ic)
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* 2011-07-24 398 1.1 support 0,2, or 3 data FIFO's
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* 2011-07-23 397 1.0 Initial version, factored out from usb_jtag_init()
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*
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*-----------------------------------------------------------------------------
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*/
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#include "fx2regs.h"
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#include "syncdelay.h"
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//-----------------------------------------------------------------------------
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void usb_fifo_init(void) // Called once at startup
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{
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// set the CPU clock to 48MHz, enable USB clock output to FPGA
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// Note: CLKOUT not connected on nexys2, nexys3 and atlys...
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CPUCS = bmCLKOE | bmCLKSPD1;
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// setup FIFO mode
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// bmIFCLKSRC clock source: 0 external clock; 1 internal clock
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// bm3048MHZ clock frequency: 0 30 MHz; 1 48 MHz
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// bmIFCLKOE IFCLK pin output enable: 0 tri-state; 1 drive
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// bmIFCLKPOL clock polarity: 0 rising edge active; 1 falling edge active
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// bmASYNC fifo mode: 0 synchrounous; 1 asynchronous
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// IFCFG interface mode: bmIFCFGMASK=11->slave fifo
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#if defined(USE_IC30)
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// Use internal 30 MHz, enable output, slave sync FIFO, slave FIFO mode
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IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmIFCFGMASK;
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#else
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// Use internal 30 MHz, enable output, slave async FIFO, slave FIFO mode
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IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC | bmIFCFGMASK;
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#endif
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// Setup PA7 as FLAGD
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PORTACFG = 0x80; SYNCDELAY; // 1000 0000: FLAGD=1, SLCS=0
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// setup usage of FLAG pins
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// goal is to support EP4(out) and EP6/EP8(in) synchronous slave fifos
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// for synchronous operation usage of empty/full and almost empty/full
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// flags is needed, the later are realized with the programmable flags.
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// the three empty/full flags are setup as fixed flags, while the three
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// almost (or programmable) flags are channeled over one indexed flag pin.
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// FLAGA = indexed, PF (the default)
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// FLAGB = EP6 FF
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// FLAGC = EP4 EF
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// FLAGD = EP8 FF
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PINFLAGSAB = 0xE0; SYNCDELAY; // 1110 0000: B EP6 FF, A indexed
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PINFLAGSCD = 0xF9; SYNCDELAY; // 1111 1001: D EP8 FF, C EP4 EF
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// define endpoint configuration
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FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all
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REVCTL = 3; SYNCDELAY; // Allow FW access to FIFO buffer
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// FIFOs used for JTAG emulation
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// EP1 IN
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// EP2 OUT
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EP1OUTCFG = 0x00; SYNCDELAY; // EP1 OUT: inactive
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EP1INCFG = 0xA0; SYNCDELAY; // EP1 IN: active, bulk
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EP2FIFOCFG = 0x00; SYNCDELAY; // EP2 slave: 0, not used as slave
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FIFORESET = 0x02; SYNCDELAY; // EP2 reset (0x02! see comment below)
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EP2CFG = 0xA2; SYNCDELAY; // EP2: 1010 0010: VAL,OUT,BULK,DOUBLE
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// TMR (Rev *D) page 117: auto in/out initialization sequence
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// Auto IN transfers
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// 1. setup EPxCFG
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// 2. reset the FIFO
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// 3. set EPxFIFOCFG.3 = 1
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// 4. set EPxAUTOINLENH:L
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// Auto OUT transfers
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// 1. setup EPxCFG
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// 2. reset the FIFO
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// 3. arm OUT buffers by writing OUTPKTEND N times w/ skip=1 (N=buf depth)
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// 4. set EPxFIFOCFG.4 = 1
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// 2 FIFOs used for DATA transfer:
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// EP4 OUT DOUBLE
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// EP6 IN QUAD
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#if defined(USE_2FIFO) || defined(USE_3FIFO)
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EP4CFG = 0xA2; SYNCDELAY; // EP4: 1010 0010: VAL,OUT,BULK,DOUBLE
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#if defined(USE_3FIFO)
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EP6CFG = 0xE2; SYNCDELAY; // EP6: 1110 0010: VAL,IN,BULK,DOUBLE
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EP8CFG = 0xE2; SYNCDELAY; // EP8: 1110 0010: VAL,IN,BULK,DOUBLE
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#else
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EP6CFG = 0xE0; SYNCDELAY; // EP6: 1110 0000: VAL,IN,BULK,QUAD
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EP8CFG = 0x02; SYNCDELAY; // EP8: disabled
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#endif
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// Note: the description of the FIFORESET in the TMR, Rev *D (2011) is
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// wrong. The TMR asks to write 0x80,0x82,0x84,0x86,0x88,0x00, e.g
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// on page 117, also in other contexts.
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// This doesn't work, FIFO's are in fact not reset !
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// The proper sequence is 0x80,0x02,0x04,0x06,0x08,0x00, as for
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// example stated in http://www.cypress.com/?id=4&rID=32093
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FIFORESET = 0x04; SYNCDELAY; // EP4 reset
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FIFORESET = 0x06; SYNCDELAY; // EP6 reset
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FIFORESET = 0x08; SYNCDELAY; // EP8 reset
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FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour
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// !! really needed here, before buffers are armed !!
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REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer
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// EP4 OUT setup ---------------------------------------------------
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OUTPKTEND = 0x84; SYNCDELAY; // arm all EP4 buffers
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OUTPKTEND = 0x84; SYNCDELAY;
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// !! hardware only arms endpoint when AUTOOUT 0->1 transition seen
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// !! --> clean AUTOOUT to handle for example back-to-back firmware loads
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EP4FIFOCFG = 0x00; SYNCDELAY; // EP4: force AUTOOUT 0->1 transition
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EP4FIFOCFG = 0x10; SYNCDELAY; // EP4: 0001 0000: AUTOOUT, BYTE
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// setup programmable fifo threshold as 'almost empty' at 3 bytes to go
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// --> keep active low logic for prgrammable flags
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// --> set flag 1 when fill >= threshold (DECIS=1)
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// --> almost empty thus at fill<4, effective threshold thus 3 !!
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EP4FIFOPFH = 0x80; SYNCDELAY; // 0000 0000: DECIS=1, PFC8=0
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EP4FIFOPFL = 0x04; SYNCDELAY; // PFC = 4 = 0 0000 0100
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// EP6 IN setup ---------------------------------------------------
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EP6FIFOCFG = 0x0C; SYNCDELAY; // EP6: 0000 1100: AUTOIN, ZEROLEN, BYTE
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EP6AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers
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EP6AUTOINLENL = 0x00; SYNCDELAY;
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// setup programmable fifo threshold as 'almost full' at 3 bytes to go
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// --> keep active low logic for prgrammable flags
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// --> set flag 1 when fill <= threshold (DECIS=0)
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// --> use full buffer fill
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// --> for dual buffered: (PKSTAT=0, PKTS=1) [in case 3 fifo's used]
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// --> for quad buffered: (PKSTAT=0, PKTS=3) [in case 2 fifo's used]
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// --> effective threshold thus 3 in both bases
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#if defined(USE_3FIFO)
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EP6FIFOPFH = 0x09; SYNCDELAY; // 0000 1001: DECIS=0, PK=0:1, PFC8=1
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#else
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EP6FIFOPFH = 0x19; SYNCDELAY; // 0001 1001: DECIS=0, PK=0:3, PFC8=1
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#endif
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EP6FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100
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#if defined(USE_3FIFO)
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// EP8 IN setup ---------------------------------------------------
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EP8FIFOCFG = 0x0C; SYNCDELAY; // EP8: 0000 1100: AUTOIN, ZEROLEN, BYTE
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EP8AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers
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EP8AUTOINLENL = 0x00; SYNCDELAY;
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// setup programmable fifo threshold as 'almost full' at 4 bytes to go
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// like for EP6 above
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EP8FIFOPFH = 0x41; SYNCDELAY; // 0100 0001: DECIS=0, PKSTAT=1, PFC8=1
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EP8FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100
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#else
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// EP8 setup
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EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave
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#endif
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#else
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// no FIFOs used for DATA transfer
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// EP4,6,8 inactive
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EP4CFG = 0x02; SYNCDELAY; // EP4: disabled
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EP6CFG = 0x02; SYNCDELAY; // EP6: disabled
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EP8CFG = 0x02; SYNCDELAY; // EP8: disabled
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FIFORESET = 0x04; SYNCDELAY; // EP4 reset
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FIFORESET = 0x06; SYNCDELAY; // EP6 reset
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FIFORESET = 0x08; SYNCDELAY; // EP8 reset
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FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour
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EP4FIFOCFG = 0x00; SYNCDELAY; // EP4 slave: 0, not used as slave
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EP6FIFOCFG = 0x00; SYNCDELAY; // EP6 slave: 0, not used as slave
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EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave
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REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer
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#endif
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// the EP2 endpoint does not come up armed. It is used with double buffering
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// so write dummy byte counts twice.
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SYNCDELAY; //
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EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT
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EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT
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}
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