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e91847f8db
- added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated
64 lines
2.0 KiB
VHDL
64 lines
2.0 KiB
VHDL
-- $Id: iob_keeper_gen.vhd 649 2015-02-21 21:10:16Z mueller $
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: iob_keeper_gen - sim
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-- Description: keeper for IOB, vector
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-06-03 299 1.1 add explicit R_KEEP and driver
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-- 2008-05-22 148 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.xlib.all;
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entity iob_keeper_gen is -- keeper for IOB, vector
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generic (
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DWIDTH : positive := 16); -- data port width
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port (
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PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
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);
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end iob_keeper_gen;
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-- Is't possible to directly use 'PAD<='H' in proc_pad. Introduced R_KEEP and
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-- the explicit driver 'PAD<=R_KEEP' to state the keeper function more clearly.
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architecture sim of iob_keeper_gen is
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signal R_KEEP : slv(DWIDTH-1 downto 0) := (others=>'W');
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begin
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proc_keep: process (PAD)
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begin
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for i in PAD'range loop
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if PAD(i) = '1' then
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R_KEEP(i) <= 'H';
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elsif PAD(i) = '0' then
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R_KEEP(i) <= 'L';
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elsif PAD(i)='X' or PAD(i)='U' then
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R_KEEP(i) <= 'W';
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end if;
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end loop;
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PAD <= R_KEEP;
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end process proc_keep;
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end sim;
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