mirror of
https://github.com/wfjm/w11.git
synced 2026-05-01 22:17:08 +00:00
e91847f8db
- added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated
268 lines
7.7 KiB
VHDL
268 lines
7.7 KiB
VHDL
-- $Id: tst_fx2loop.vhd 649 2015-02-21 21:10:16Z mueller $
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--
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-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tst_fx2loop - syn
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-- Description: simple stand-alone tester for fx2lib components
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--
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-- Dependencies: comlib/byte2word
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-- comlib/word2byte
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next
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-- 2012-01-15 453 1.0 Initial version
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-- 2011-12-26 445 0.5 First draft
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.comlib.all;
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use work.fx2lib.all;
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use work.tst_fx2looplib.all;
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-- ----------------------------------------------------------------------------
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entity tst_fx2loop is -- tester for fx2lib components
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CE_MSEC : in slbit; -- msec pulse
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HIO_CNTL : in hio_cntl_type; -- humanio controls
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HIO_STAT : out hio_stat_type; -- humanio status
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FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
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RXDATA : in slv8; -- receiver data out
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RXVAL : in slbit; -- receiver data valid
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RXHOLD : out slbit; -- receiver data hold
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TXDATA : out slv8; -- transmit data in
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TXENA : out slbit; -- transmit data enable
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TXBUSY : in slbit; -- transmit busy
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TX2DATA : out slv8; -- transmit 2 data in
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TX2ENA : out slbit; -- transmit 2 data enable
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TX2BUSY : in slbit -- transmit 2 busy
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);
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end tst_fx2loop;
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architecture syn of tst_fx2loop is
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type regs_type is record
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rxdata : slv16; -- next rx word
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txdata : slv16; -- next tx word
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tx2data : slv16; -- next tx2 word
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rxsecnt : slv16; -- rx sequence error counter
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rxcnt : slv32; -- rx word counter
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txcnt : slv32; -- tx word counter
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tx2cnt : slv32; -- tx2 word counter
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rxthrottle : slbit; -- rx throttle flag
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end record regs_type;
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constant regs_init : regs_type := (
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(others=>'0'), -- rxdata
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(others=>'0'), -- txdata
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(others=>'0'), -- tx2data
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(others=>'0'), -- rxsecnt
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(others=>'0'), -- rxcnt
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(others=>'0'), -- txcnt
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(others=>'0'), -- tx2cnt
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'0' -- rxthrottle
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal RXWDATA : slv16 := (others=>'0');
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signal RXWVAL : slbit := '0';
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signal RXWHOLD : slbit := '0';
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signal RXODD : slbit := '0';
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signal TXWDATA : slv16 := (others=>'0');
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signal TXWENA : slbit := '0';
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signal TXWBUSY : slbit := '0';
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signal TXODD : slbit := '0';
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signal TX2WDATA : slv16 := (others=>'0');
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signal TX2WENA : slbit := '0';
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signal TX2WBUSY : slbit := '0';
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signal TX2ODD : slbit := '0';
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signal RXHOLD_L : slbit := '0'; -- local copy of out port signal
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signal TXENA_L : slbit := '0'; -- local copy of out port signal
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signal TX2ENA_L : slbit := '0'; -- local copy of out port signal
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signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal
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begin
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CNTL_RESET_L <= '0'; -- so far unused
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RXB2W : byte2word
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port map (
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CLK => CLK,
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RESET => CNTL_RESET_L,
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DI => RXDATA,
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ENA => RXVAL,
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BUSY => RXHOLD_L,
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DO => RXWDATA,
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VAL => RXWVAL,
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HOLD => RXWHOLD,
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ODD => RXODD
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);
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TX1W2B : word2byte
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port map (
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CLK => CLK,
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RESET => CNTL_RESET_L,
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DI => TXWDATA,
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ENA => TXWENA,
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BUSY => TXWBUSY,
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DO => TXDATA,
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VAL => TXENA_L,
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HOLD => TXBUSY,
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ODD => TXODD
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);
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TX2W2B : word2byte
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port map (
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CLK => CLK,
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RESET => CNTL_RESET_L,
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DI => TX2WDATA,
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ENA => TX2WENA,
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BUSY => TX2WBUSY,
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DO => TX2DATA,
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VAL => TX2ENA_L,
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HOLD => TX2BUSY,
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ODD => TX2ODD
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);
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI,
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RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY,
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RXHOLD_L, TXBUSY, TX2BUSY)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable irxwhold : slbit := '1';
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variable itxwena : slbit := '0';
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variable itxwdata : slv16 := (others=>'0');
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variable itx2wena : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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irxwhold := '1';
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itxwena := '0';
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itxwdata := RXWDATA;
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itx2wena := '0';
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if HIO_CNTL.throttle = '1' then
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if CE_MSEC = '1' then
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n.rxthrottle := not r.rxthrottle;
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end if;
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else
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n.rxthrottle := '0';
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end if;
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case HIO_CNTL.mode is
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when c_mode_idle =>
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null;
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when c_mode_rxblast =>
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if RXWVAL='1' and r.rxthrottle='0' then
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irxwhold := '0';
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if RXWDATA /= r.rxdata then
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n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
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end if;
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n.rxdata := slv(unsigned(RXWDATA) + 1);
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end if;
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when c_mode_txblast =>
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itxwdata := r.txdata;
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if TXWBUSY = '0' then
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itxwena := '1';
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n.txdata := slv(unsigned(r.txdata) + 1);
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end if;
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irxwhold := '0';
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when c_mode_loop =>
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itxwdata := RXWDATA;
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if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then
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irxwhold := '0';
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itxwena := '1';
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end if;
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when others => null;
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end case;
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if HIO_CNTL.tx2blast = '1' then
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if TX2WBUSY = '0' then
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itx2wena := '1';
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n.tx2data := slv(unsigned(r.tx2data) + 1);
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end if;
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end if;
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if RXWVAL='1' and irxwhold='0' then
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n.rxcnt := slv(unsigned(r.rxcnt) + 1);
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end if;
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if itxwena = '1' then
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n.txcnt := slv(unsigned(r.txcnt) + 1);
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end if;
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if itx2wena = '1' then
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n.tx2cnt := slv(unsigned(r.tx2cnt) + 1);
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end if;
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N_REGS <= n;
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RXWHOLD <= irxwhold;
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TXWENA <= itxwena;
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TXWDATA <= itxwdata;
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TX2WENA <= itx2wena;
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TX2WDATA <= r.tx2data;
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HIO_STAT.rxhold <= RXHOLD_L;
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HIO_STAT.txbusy <= TXBUSY;
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HIO_STAT.tx2busy <= TX2BUSY;
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HIO_STAT.rxsecnt <= r.rxsecnt;
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HIO_STAT.rxcnt <= r.rxcnt;
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HIO_STAT.txcnt <= r.txcnt;
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HIO_STAT.tx2cnt <= r.tx2cnt;
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end process proc_next;
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RXHOLD <= RXHOLD_L;
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TXENA <= TXENA_L;
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TX2ENA <= TX2ENA_L;
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end syn;
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