mirror of
https://github.com/wfjm/w11.git
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cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
173 lines
8.9 KiB
VHDL
173 lines
8.9 KiB
VHDL
-- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $
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--
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-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: fx2lib
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-- Description: Cypress ez-usb fx2 support
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--
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-- Dependencies: -
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-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
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-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
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-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
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-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as
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-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type
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-- 2011-07-07 389 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package fx2lib is
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constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2
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constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4
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constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6
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constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8
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type fx2ctl_moni_type is record -- fx2ctl monitor port
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fifo_ep4 : slbit; -- fifo 1 (ep4) active;
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fifo_ep6 : slbit; -- fifo 2 (ep6) active;
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fifo_ep8 : slbit; -- fifo 3 (ep8) active;
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flag_ep4_empty : slbit; -- ep4 empty flag (latched);
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flag_ep4_almost : slbit; -- ep4 almost empty flag (latched);
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flag_ep6_full : slbit; -- ep6 full flag (latched);
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flag_ep6_almost : slbit; -- ep6 almost full flag (latched);
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flag_ep8_full : slbit; -- ep8 full flag (latched);
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flag_ep8_almost : slbit; -- ep8 almost full flag (latched);
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slrd : slbit; -- read strobe
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slwr : slbit; -- write strobe
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pktend : slbit; -- pktend strobe
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end record fx2ctl_moni_type;
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constant fx2ctl_moni_init : fx2ctl_moni_type := (
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'0','0','0', -- fifo_ep[468]
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'0','0', -- flag_ep4_(empty|almost)
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'0','0', -- flag_ep6_(full|almost)
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'0','0', -- flag_ep8_(full|almost)
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'0','0','0' -- slrd, slwr, pktend
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);
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-- -------------------------------------
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component fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
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generic (
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RXFAWIDTH : positive := 5; -- receive fifo address width
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TXFAWIDTH : positive := 5; -- transmit fifo address width
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PETOWIDTH : positive := 7; -- packet end time-out counter width
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CCWIDTH : positive := 5; -- chunk counter width
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RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
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TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
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RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
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RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
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WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
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WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
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FLAGDELAY : positive := 2); -- flag delay in clock cycles
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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RESET : in slbit := '0'; -- reset
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RXDATA : out slv8; -- receive data out
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RXVAL : out slbit; -- receive data valid
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RXHOLD : in slbit; -- receive data hold
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RXAEMPTY : out slbit; -- receive almost empty flag
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit data busy
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TXAFULL : out slbit; -- transmit almost full flag
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MONI : out fx2ctl_moni_type; -- monitor port data
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end component;
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component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
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generic (
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RXFAWIDTH : positive := 5; -- receive fifo address width
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TXFAWIDTH : positive := 5; -- transmit fifo address width
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PETOWIDTH : positive := 7; -- packet end time-out counter width
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CCWIDTH : positive := 5; -- chunk counter width
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RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
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TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RXDATA : out slv8; -- receive data out
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RXVAL : out slbit; -- receive data valid
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RXHOLD : in slbit; -- receive data hold
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RXAEMPTY : out slbit; -- receive almost empty flag
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit data busy
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TXAFULL : out slbit; -- transmit almost full flag
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MONI : out fx2ctl_moni_type; -- monitor port data
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end component;
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component fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
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generic (
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RXFAWIDTH : positive := 5; -- receive fifo address width
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TXFAWIDTH : positive := 5; -- transmit fifo address width
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PETOWIDTH : positive := 7; -- packet end time-out counter width
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CCWIDTH : positive := 5; -- chunk counter width
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RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
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TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
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TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RXDATA : out slv8; -- receive data out
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RXVAL : out slbit; -- receive data valid
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RXHOLD : in slbit; -- receive data hold
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RXAEMPTY : out slbit; -- receive almost empty flag
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TXDATA : in slv8; -- transmit 1 data in
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TXENA : in slbit; -- transmit 1 data enable
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TXBUSY : out slbit; -- transmit 1 data busy
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TXAFULL : out slbit; -- transmit 1 almost full flag
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TX2DATA : in slv8; -- transmit 2 data in
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TX2ENA : in slbit; -- transmit 2 data enable
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TX2BUSY : out slbit; -- transmit 2 data busy
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TX2AFULL : out slbit; -- transmit 2 almost full flag
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MONI : out fx2ctl_moni_type; -- monitor port data
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end component;
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end package fx2lib;
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