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3f455d5236
- re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std
131 lines
3.8 KiB
VHDL
131 lines
3.8 KiB
VHDL
-- $Id: pdp11_sys70.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_sys70 - syn
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-- Description: pdp11: 11/70 system registers
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.1.1 now numeric_std clean
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-- 2010-10-17 333 1.1 use ibus V2 interface
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-- 2008-08-22 161 1.0.1 use iblib
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-- 2008-04-20 137 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.pdp11.all;
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use work.iblib.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_sys70 is -- 11/70 memory system registers
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port (
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CLK : in slbit; -- clock
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CRESET : in slbit; -- console reset
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type -- ibus response
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);
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end pdp11_sys70;
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architecture syn of pdp11_sys70 is
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constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16));
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constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16));
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type regs_type is record -- state registers
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ibsel_mbrk : slbit; -- ibus select mbrk
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ibsel_sysid : slbit; -- ibus select sysid
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mbrk : slv8; -- status of mbrk register
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end record regs_type;
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constant regs_init : regs_type := (
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'0','0', -- ibsel_*
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mbrk=>(others=>'0') -- mbrk
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if CRESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, IB_MREQ)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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variable ibw0 : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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idout := (others=>'0');
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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-- ibus address decoder
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n.ibsel_mbrk := '0';
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n.ibsel_sysid := '0';
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if IB_MREQ.aval = '1' then
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if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then
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n.ibsel_mbrk := '1';
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end if;
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if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then
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n.ibsel_sysid := '1';
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end if;
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end if;
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-- ibus transactions
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if r.ibsel_mbrk = '1' then
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idout(r.mbrk'range) := r.mbrk;
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end if;
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if r.ibsel_sysid = '1' then
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idout := slv(to_unsigned(8#123456#,16));
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end if;
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if r.ibsel_mbrk='1' and ibw0='1' then
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n.mbrk := IB_MREQ.din(n.mbrk'range);
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end if;
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N_REGS <= n;
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IB_SRES.dout <= idout;
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IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq;
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IB_SRES.busy <= '0';
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end process proc_next;
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end syn;
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