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14362b2a56
- arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model
122 lines
6.4 KiB
VHDL
122 lines
6.4 KiB
VHDL
-- $Id: miglib_arty.vhd 1093 2018-12-25 19:52:53Z mueller $
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--
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-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: miglib_arty
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-- Description: MIG interface components - for arty
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--
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-- Dependencies: -
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-- Tool versions: viv 2017.2; ghdl 0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2018-11-17 1071 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.miglib.all;
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package miglib_arty is
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constant mig_bawidth : positive := 4; -- byte addr width
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constant mig_mawidth : positive := 28; -- mem addr width
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constant mig_mwidth : positive := 2**mig_bawidth; -- mask width ( 16)
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constant mig_dwidth : positive := 8*mig_mwidth; -- data width (128)
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component sramif_mig_arty is -- SRAM to DDR via MIG for arty
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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REQ : in slbit; -- request
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WE : in slbit; -- write enable
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BUSY : out slbit; -- controller busy
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ACK_R : out slbit; -- acknowledge read
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ACK_W : out slbit; -- acknowledge write
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ACT_R : out slbit; -- signal active read
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ACT_W : out slbit; -- signal active write
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ADDR : in slv20; -- address (32 bit word address)
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BE : in slv4; -- byte enable
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DI : in slv32; -- data in (memory view)
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DO : out slv32; -- data out (memory view)
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CLKMIG : in slbit; -- sys clock for mig core
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CLKREF : in slbit; -- ref clock for mig core
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TEMP : in slv12; -- die temperature
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MONI : out sramif2migui_moni_type;-- monitor signals
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DDR3_DQ : inout slv16; -- dram: data in/out
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DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
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DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
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DDR3_ADDR : out slv14; -- dram: address
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DDR3_BA : out slv3; -- dram: bank address
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DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
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DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
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DDR3_WE_N : out slbit; -- dram: write enable (act.low)
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DDR3_RESET_N : out slbit; -- dram: reset (act.low)
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DDR3_CK_P : out slv1; -- dram: clock (diff-p)
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DDR3_CK_N : out slv1; -- dram: clock (diff-n)
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DDR3_CKE : out slv1; -- dram: clock enable
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DDR3_CS_N : out slv1; -- dram: chip select (act.low)
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DDR3_DM : out slv2; -- dram: data input mask
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DDR3_ODT : out slv1 -- dram: on-die termination
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);
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end component;
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component migui_arty is -- MIG generated for arty
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port (
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DDR3_DQ : inout slv16; -- dram: data in/out
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DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
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DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
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DDR3_ADDR : out slv14; -- dram: address
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DDR3_BA : out slv3; -- dram: bank address
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DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
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DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
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DDR3_WE_N : out slbit; -- dram: write enable (act.low)
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DDR3_RESET_N : out slbit; -- dram: reset (act.low)
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DDR3_CK_P : out slv1; -- dram: clock (diff-p)
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DDR3_CK_N : out slv1; -- dram: clock (diff-n)
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DDR3_CKE : out slv1; -- dram: clock enable
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DDR3_CS_N : out slv1; -- dram: chip select (act.low)
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DDR3_DM : out slv2; -- dram: data input mask
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DDR3_ODT : out slv1; -- dram: on-die termination
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APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
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APP_CMD : in slv3; -- MIGUI command
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APP_EN : in slbit; -- MIGUI command enable
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APP_WDF_DATA : in slv(mig_dwidth-1 downto 0); -- MIGUI write data
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APP_WDF_END : in slbit; -- MIGUI write end
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APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
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APP_WDF_WREN : in slbit; -- MIGUI write enable
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APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
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APP_RD_DATA_END : out slbit; -- MIGUI read end
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APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
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APP_RDY : out slbit; -- MIGUI ready for cmd
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APP_WDF_RDY : out slbit; -- MIGUI ready for data write
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APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
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APP_REF_REQ : in slbit; -- MIGUI refresh reques
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APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
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APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
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APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
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APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
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UI_CLK : out slbit; -- MIGUI clock
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UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
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INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
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SYS_CLK_I : in slbit; -- MIGUI system clock
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CLK_REF_I : in slbit; -- MIGUI reference clock
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DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
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SYS_RST : in slbit -- MIGUI system reset
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);
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end component;
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end package miglib_arty;
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