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https://github.com/wfjm/w11.git
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14362b2a56
- arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model
42 lines
1.1 KiB
Makefile
42 lines
1.1 KiB
Makefile
# $Id: Makefile 1063 2018-10-29 18:37:42Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-06-18 776 1.1.1 add xsim_clean
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# 2016-04-22 763 1.1 add include dep_vsim
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# 2016-01-31 726 1.0 Initial version
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#
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EXE_all = tb_arty_dummy tb_arty_dram_dummy
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#
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include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk
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#
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.PHONY : all all_ssim all_osim clean
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.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
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#
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all : $(EXE_all)
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all_ssim : $(EXE_all:=_ssim)
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all_osim : $(EXE_all:=_osim)
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#
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all_XSim : $(EXE_all:=_XSim)
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all_XSim_ssim : $(EXE_all:=_XSim_ssim)
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all_XSim_osim : $(EXE_all:=_XSim_osim)
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all_XSim_tsim : $(EXE_all:=_XSim_tsim)
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#
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clean : viv_clean ghdl_clean xsim_clean
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#
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#-----
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#
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include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
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include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
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include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
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#
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VBOM_all = $(wildcard *.vbom)
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#
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ifndef DONTINCDEP
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include $(VBOM_all:.vbom=.dep_vsyn)
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include $(VBOM_all:.vbom=.dep_ghdl)
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include $(VBOM_all:.vbom=.dep_vsim)
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include $(wildcard *.o.dep_ghdl)
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endif
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#
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