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120 lines
6.1 KiB
Plaintext
120 lines
6.1 KiB
Plaintext
# $Id: sys_w11a_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
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#
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# Validated code/tool version combinations
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# Date rev viv
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# 2019-02-02 1108 2017.2
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# 2019-02-02 1108 2018.3
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#
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# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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[syn]
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# general issues -----------------------------------------------
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{2018.2:}
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# stupid new warning, Xilinx suggests to safely ingnore
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i [Constraints 18-5210] # generic
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{:}
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# binding instance .. which has no pins ------------------------
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I [Synth 8-115] # generic
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# false_path -hold ignored by synth ----------------------------
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I [Designutils 20-1567] # generic
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# net without driver -------------------------------------------
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# unconnected ports --------------------------------------------
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I [Synth 8-3331] IB_MREQ # generic
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I [Synth 8-3331] RB_MREQ # generic
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I [Synth 8-3331] DM_STAT_CO # generic
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I [Synth 8-3331] DM_STAT_DP # generic
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I [Synth 8-3331] DM_STAT_EXP # generic
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I [Synth 8-3331] DM_STAT_SE # generic
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I [Synth 8-3331] DM_STAT_VM # generic
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I [Synth 8-3331] CP_STAT # generic
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I [Synth 8-3331] SER_MONI # generic
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# --> ireg indeed not fully used # OK 2018-12-28
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i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)]
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# --> ccin indedd not fully used # OK 2018-12-28
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i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
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# --> some psr bits are used # OK 2018-12-28
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i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
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# --> not all moni fields used # OK 2018-12-28
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i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
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# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-12-28
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i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
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i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
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# --> so far no usage of usec and msec pulse # OK 2018-12-28
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i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
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# --> msec indeed not used # OK 2018-12-28
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i [Synth 8-3331] ibdr_rl11 .* CE_MSEC
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# --> ei_ack not used, interrupt request cleared via register # OK 2018-12-28
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i [Synth 8-3331] ibdr_deuna .* EI_ACK
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i [Synth 8-3331] ibd_iist .* EI_ACK
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# --> data end marker not used # OK 2019-01-02
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i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END
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# sequential element removed (2017.1 nonsense) -----------------
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I [Synth 8-6014] _reg # generic
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# unused sequential element ------------------------------------
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{2017.2:2018.2}
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I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
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# --> many HIO pins not used # OK 2018-12-28
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I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
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i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
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i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
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# --> usec not used for serport clock domain # OK 2018-12-28
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i [Synth 8-3332] R_REGS_reg[usec]
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# --> indeed no types with [3] set # OK 2018-12-28
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i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
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# --> not yet used # OK 2018-12-28
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i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
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i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
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# --> monitor outputs moneop,monattn currently not used # OK 2018-12-28
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i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
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i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
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# --> inst_compl logic disabled in pdp11_mmu # OK 2018-12-28
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i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
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# --> not yet used # OK 2018-12-28
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i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
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# --> [8] is for DZ11TX, not yet available # OK 2018-12-28
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# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
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i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
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# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-12-28
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i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
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# --> scnt disabled, thus 3 SNUM bits '0' # OK 2018-12-28
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i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
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{:}
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# INFO: encoded FSM with state register as --------------------
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# test for sys_w11a_br_arty that all FSMs are one_hot
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r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'
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r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox'
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r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11'
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r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core'
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# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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[imp]
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I [Vivado 12-2489] # multiple of 1 ps
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I [Physopt 32-742] # BRAM Flop Optimization
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{:2017.2}
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# --> spurious Invalid VCCINTIO messages # OK 2018-12-28
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i [Designutils 20-266] Invalid Voltage Source VCCINTIO
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{:}
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# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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[bit]
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# see https://www.xilinx.com/support/answers/64180.html # OK 2018-12-28
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i [DRC REQP-1709] PLLE2_ADV
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# --> DSP multiplier is not pipelined, ok # OK 2018-12-28
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i [DRC DPOP-1] PREG Output pipelining
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i [DRC DPOP-2] MREG Output pipelining
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