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https://github.com/wfjm/w11.git
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e91847f8db
- added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated
91 lines
2.3 KiB
VHDL
91 lines
2.3 KiB
VHDL
-- $Id: gray_cnt_gen.vhd 649 2015-02-21 21:10:16Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: gray_cnt_gen - syn
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-- Description: Generic width Gray code counter
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-26 106 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.genlib.all;
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entity gray_cnt_gen is -- gray code counter, generic vector
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generic (
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DWIDTH : positive := 4); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv(DWIDTH-1 downto 0) -- data out
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);
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end entity gray_cnt_gen;
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architecture syn of gray_cnt_gen is
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begin
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assert DWIDTH>=4
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report "assert(DWIDTH>=4): only 4 or more bit width supported"
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severity failure;
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GRAY_4: if DWIDTH=4 generate
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begin
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CNT : gray_cnt_4
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port map (
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CLK => CLK,
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RESET => RESET,
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CE => CE,
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DATA => DATA
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);
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end generate GRAY_4;
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GRAY_5: if DWIDTH=5 generate
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begin
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CNT : gray_cnt_5
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port map (
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CLK => CLK,
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RESET => RESET,
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CE => CE,
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DATA => DATA
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);
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end generate GRAY_5;
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GRAY_N: if DWIDTH>5 generate
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begin
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CNT : gray_cnt_n
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generic map (
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DWIDTH => DWIDTH)
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port map (
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CLK => CLK,
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RESET => RESET,
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CE => CE,
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DATA => DATA
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);
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end generate GRAY_N;
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end syn;
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