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https://github.com/wfjm/w11.git
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e91847f8db
- added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated
95 lines
3.0 KiB
VHDL
95 lines
3.0 KiB
VHDL
-- $Id: fifo_1c_dram.vhd 641 2015-02-01 22:12:15Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: fifo_1c_dram - syn
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-- Description: FIFO, single clock domain, distributed RAM based, with
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-- enable/busy/valid/hold interface.
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--
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-- Dependencies: fifo_1c_dram_raw
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--
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-- Test bench: tb/tb_fifo_1c_dram
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-06-06 49 1.0 Initial version
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--
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-- Some synthesis results:
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-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
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-- AWIDTH DWIDTH LUT.l LUT.m Flop clock(xst est.)
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-- 4 16 31 32 22 153MHz ( 16 words)
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-- 5 16 49 64 23 120MHz ( 32 words)
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-- 6 16 70 128 23 120MHz ( 64 words)
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-- 7 16 111 256 30 120MHz (128 words)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.memlib.all;
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entity fifo_1c_dram is -- fifo, 1 clock, dram based
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generic (
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AWIDTH : positive := 7; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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DI : in slv(DWIDTH-1 downto 0); -- input data
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ENA : in slbit; -- write enable
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BUSY : out slbit; -- write port hold
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DO : out slv(DWIDTH-1 downto 0); -- output data
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VAL : out slbit; -- read valid
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HOLD : in slbit; -- read hold
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SIZE : out slv(AWIDTH downto 0) -- number of used slots
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);
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end fifo_1c_dram;
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architecture syn of fifo_1c_dram is
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signal WE : slbit := '0';
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signal RE : slbit := '0';
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signal SIZE_L : slv(AWIDTH-1 downto 0) := (others=>'0');
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signal EMPTY : slbit := '0';
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signal FULL : slbit := '0';
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begin
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FIFO : fifo_1c_dram_raw
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generic map (
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AWIDTH => AWIDTH,
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DWIDTH => DWIDTH)
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port map (
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CLK => CLK,
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RESET => RESET,
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WE => WE,
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RE => RE,
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DI => DI,
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DO => DO,
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SIZE => SIZE_L,
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EMPTY => EMPTY,
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FULL => FULL
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);
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WE <= ENA and (not FULL);
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RE <= (not EMPTY) and (not HOLD);
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BUSY <= FULL;
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VAL <= not EMPTY;
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SIZE <= FULL & SIZE_L;
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end syn;
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