mirror of
https://github.com/wfjm/w11.git
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cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
285 lines
6.8 KiB
C
285 lines
6.8 KiB
C
/* $Id: hw_nexys2.c 447 2011-12-31 19:41:32Z mueller $ */
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/*
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* Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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* Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
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*
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* - original copyright and licence disclaimer --------------------------------
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* - Copyright (C) 2007 Kolja Waschk, ixo.de
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* - This code is part of usbjtag. usbjtag is free software;
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* - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2)
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* - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling
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* - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you may redistribute and/or modify it under
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* the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 2, or at your option any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for complete details.
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*
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* ----------------------------------------------------------------------------
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* Hardware-dependent code for usb_jtag
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*
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* Revision History:
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*
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* Date Rev Version Comment
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* 2011-12-30 447 1.2.1 move JTAG pin OE intoProgIO_Set_State()
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* 2011-12-29 446 1.2 clean-out all code not relevant for nexys2
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* 2011-07-23 397 1.1 move IFCONFIG and CPUCS init to usb_fifo_init
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* 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)
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*
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*-----------------------------------------------------------------------------
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*/
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#include <fx2regs.h>
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#include "hardware.h"
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#include "delay.h"
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//-----------------------------------------------------------------------------
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/* JTAG TCK, AS/PS DCLK */
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sbit at 0xB4 TCK; /* Port D.4 */
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#define bmTCKOE bmBIT4
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#define SetTCK(x) do{TCK=(x);}while(0)
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/* JTAG TDI, AS ASDI, PS DATA0 */
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sbit at 0xB2 TDI; /* Port D.2 */
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#define bmTDIOE bmBIT2
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#define SetTDI(x) do{TDI=(x);}while(0)
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/* JTAG TMS, AS/PS nCONFIG */
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sbit at 0xB3 TMS; /* Port D.3 */
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#define bmTMSOE bmBIT3
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#define SetTMS(x) do{TMS=(x);}while(0)
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/* JTAG TDO, AS/PS CONF_DONE */
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sbit at 0xB0 TDO; /* Port D.0 */
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#define bmTDOOE bmBIT0
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#define GetTDO(x) TDO
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/* USB Power-On (Nexys2 specific !!) */
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sbit at 0xB7 USBPOW; /* Port D.7 */
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#define bmUSBPOWOE bmBIT7
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#define SetUSBPOW(x) do{USBPOW=(x);}while(0)
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//-----------------------------------------------------------------------------
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#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE)
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#define bmPROGINOE (bmTDOOE)
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//-----------------------------------------------------------------------------
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void ProgIO_Poll(void) {}
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void ProgIO_Enable(void) {}
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// These aren't called anywhere in usbjtag.c so far, might come...
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void ProgIO_Disable(void) {}
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void ProgIO_Deinit(void) {}
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void ProgIO_Init(void)
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{
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/* The following code depends on your actual circuit design.
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Make required changes _before_ you try the code! */
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// power on the onboard FPGA:
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// output enable and set to 1 the Nexys2 USB-Power-enable signal
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SetUSBPOW(1);
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OED=bmUSBPOWOE;
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// Note: JTAG signal output enables are in ProgIO_Set_State() below.
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mdelay(500); // wait for supply to come up
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}
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void ProgIO_Set_State(unsigned char d)
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{
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/* Set state of output pins:
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*
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* d.0 => TCK
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* d.1 => TMS
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* d.4 => TDI
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*/
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// JTAG signal output enables done at first request:
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// this allows to use the JTAG connector with another JTAG cable
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// alternatively.
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OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable
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SetTCK((d & bmBIT0) ? 1 : 0);
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SetTMS((d & bmBIT1) ? 1 : 0);
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SetTDI((d & bmBIT4) ? 1 : 0);
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}
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//-----------------------------------------------------------------------------
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// dummied AS/PS code
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#define GetASDO(x) 1
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unsigned char ProgIO_Set_Get_State(unsigned char d)
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{
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/* Set state of output pins (s.a.)
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* then read state of input pins:
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*
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* TDO => d.0
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* DATAOUT => d.1 (only #ifdef HAVE_AS_MODE)
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*/
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ProgIO_Set_State(d);
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return (GetASDO()<<1)|GetTDO();
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}
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//-----------------------------------------------------------------------------
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void ProgIO_ShiftOut(unsigned char c)
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{
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/* Shift out byte C:
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*
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* 8x {
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* Output least significant bit on TDI
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* Raise TCK
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* Shift c right
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* Lower TCK
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* }
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*/
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(void)c; /* argument passed in DPL */
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_asm
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MOV A,DPL
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;; Bit0
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RRC A
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MOV _TDI,C
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SETB _TCK
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;; Bit1
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RRC A
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CLR _TCK
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MOV _TDI,C
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SETB _TCK
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;; Bit2
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RRC A
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CLR _TCK
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MOV _TDI,C
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SETB _TCK
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;; Bit3
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RRC A
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CLR _TCK
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MOV _TDI,C
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SETB _TCK
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;; Bit4
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RRC A
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CLR _TCK
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MOV _TDI,C
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SETB _TCK
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;; Bit5
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RRC A
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CLR _TCK
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MOV _TDI,C
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SETB _TCK
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;; Bit6
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RRC A
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CLR _TCK
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MOV _TDI,C
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SETB _TCK
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;; Bit7
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RRC A
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CLR _TCK
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MOV _TDI,C
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SETB _TCK
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NOP
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CLR _TCK
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ret
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_endasm;
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}
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/*
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;; For ShiftInOut, the timing is a little more
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;; critical because we have to read _TDO/shift/set _TDI
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;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz
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;; is just like 50% at 6 Mhz, and that's still acceptable
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*/
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unsigned char ProgIO_ShiftInOut(unsigned char c)
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{
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/* Shift out byte C, shift in from TDO:
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*
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* 8x {
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* Read carry from TDO
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* Output least significant bit on TDI
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* Raise TCK
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* Shift c right, append carry (TDO) at left
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* Lower TCK
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* }
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* Return c.
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*/
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(void)c; /* argument passed in DPL */
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_asm
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MOV A,DPL
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;; Bit0
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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CLR _TCK
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;; Bit1
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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CLR _TCK
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;; Bit2
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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CLR _TCK
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;; Bit3
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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CLR _TCK
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;; Bit4
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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CLR _TCK
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;; Bit5
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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CLR _TCK
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;; Bit6
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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CLR _TCK
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;; Bit7
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MOV C,_TDO
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RRC A
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MOV _TDI,C
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SETB _TCK
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NOP
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CLR _TCK
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MOV DPL,A
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ret
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_endasm;
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/* return value in DPL */
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return c;
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}
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