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wfjm.w11/rtl
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wfjm 563e230a6a get Nexys A7 working and integrated 
- rtl/bplib
  - arty/migui_arty_gsim.vhd: cosmetics
  - nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
  - nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
  - tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
  - tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
  - w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
  - */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
  - sys_w11a_arty_setup.tcl: add missing memsize definition
  - sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
2019-08-10 19:03:47 +02:00
..
bplib
get Nexys A7 working and integrated
2019-08-10 19:03:47 +02:00
ibus
SPDX: rtl/*/*.vhd
2019-07-12 19:01:49 +02:00
make_ise
SPDX: *.mk
2019-07-05 17:20:44 +02:00
make_viv
SPDX: *.mk
2019-07-05 17:20:44 +02:00
sys_gen
get Nexys A7 working and integrated
2019-08-10 19:03:47 +02:00
vlib
SPDX: rest
2019-07-26 18:06:36 +02:00
w11a
SPDX: tb/*/tb_*.dat ect
2019-07-26 18:04:45 +02:00
.gitignore
re-organize .gitignores
2016-12-17 20:18:29 +01:00
README.md
docu tune-ups; some more README.md
2016-12-23 15:51:48 +01:00

README.md

This directory tree contains all HDL sources and is organized in

Directory Content
bplib support modules for boards or parts
ibus w11 ibus devices
make_ise make includes for ISE build flows
make_viv make includes for Vivado build flows
sys_gen HDL sources for top level designs
vlib wide range of support modules
w11a HDL sources for w11a core