mirror of
https://github.com/wfjm/w11.git
synced 2026-01-25 12:15:40 +00:00
563e230a6a
- rtl/bplib
- arty/migui_arty_gsim.vhd: cosmetics
- nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
- nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
- tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
- tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
- w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
- */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
- sys_w11a_arty_setup.tcl: add missing memsize definition
- sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
This directory sub-tree contains HDL sources for top level designs and is organized in
| Directory | Content | s3 | n2 | n3 | atl | n4 | n4d | arty | as7 | b3 | c7 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| tst_mig | MIG core tester | - | - | - | - | - | y | y | - | - | - |
| tst_rlink | rlink tester (over serial links) | y | y | y | - | y | y | y | - | y | y |
| tst_rlink_cuff | rlink tester (over Cypress FX2) | - | y | y | y | - | - | - | - | - | - |
| tst_serloop | serial port loop back tester | y | y | y | - | y | y | - | - | - | - |
| tst_snhumanio | Digilent board human IO tester | y | y | y | y | y | y | - | - | y | - |
| tst_sram | memory tester | y | y | y | - | y | y | y | - | - | y |
| w11a | w11a systems | y | y | y | - | y | y | y | y | y | y |