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127 lines
6.2 KiB
VHDL
127 lines
6.2 KiB
VHDL
-- $Id: s3boardlib.vhd 911 2017-06-11 10:52:32Z mueller $
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: s3boardlib
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-- Description: S3BOARD components
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--
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-- Dependencies: -
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-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib
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-- 2011-07-08 390 1.3.4 move s3_(dispdrv|humanio*) to bpgenlib
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-- 2011-07-03 387 1.3.3 move s3_rs232_iob_(int|ext) to bpgenlib
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-- 2010-12-30 351 1.3.2 use rblib; rename human s3_humanio_rri -> _rbus
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-- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50
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-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib)
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-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_
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-- 2010-05-16 291 1.2.1 rename memctl_s3sram -> s3_sram_memctl; _usp->_fusp
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-- 2010-05-01 286 1.2 added s3board_usp_aif (base+pm1_rs232)
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-- 2010-04-17 278 1.1.6 rename, prefix dispdrv,sram_summy with s3_;
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-- add s3_rs232_iob_(int|ext|int_ext)
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-- 2010-04-11 276 1.1.5 add DEBOUNCE for s3_humanio
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-- 2010-04-10 275 1.1.4 add s3_humanio
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-- 2008-02-17 117 1.1.3 memctl_s3sram: use req,we interface
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-- 2008-01-20 113 1.1.2 rename memdrv -> memctl_s3sram
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-- 2007-12-16 101 1.1.1 use _N for active low
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-- 2007-12-09 100 1.1 add sram memory signals; sram_dummy; memdrv
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-- 2007-09-23 84 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package s3boardlib is
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component s3board_aif is -- S3BOARD, abstract iface, base
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port (
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I_CLK50 : in slbit; -- 50 MHz board clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- s3 switches
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I_BTN : in slv4; -- s3 buttons
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O_LED : out slv8; -- s3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv18; -- sram: address lines
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IO_MEM_DATA : inout slv32 -- sram: data lines
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);
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end component;
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component s3board_fusp_aif is -- S3BOARD, abstract iface, base+fusp
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port (
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I_CLK50 : in slbit; -- 50 MHz board clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- s3 switches
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I_BTN : in slv4; -- s3 buttons
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O_LED : out slv8; -- s3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv18; -- sram: address lines
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IO_MEM_DATA : inout slv32; -- sram: data lines
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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);
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end component;
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component s3_sram_dummy is -- SRAM protection dummy
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port (
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv18; -- sram: address lines
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IO_MEM_DATA : inout slv32 -- sram: data lines
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);
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end component;
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component s3_sram_memctl is -- SRAM controller
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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REQ : in slbit; -- request
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WE : in slbit; -- write enable
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BUSY : out slbit; -- controller busy
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ACK_R : out slbit; -- acknowledge read
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ACK_W : out slbit; -- acknowledge write
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ACT_R : out slbit; -- signal active read
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ACT_W : out slbit; -- signal active write
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ADDR : in slv18; -- address
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BE : in slv4; -- byte enable
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DI : in slv32; -- data in (memory view)
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DO : out slv32; -- data out (memory view)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv18; -- sram: address lines
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IO_MEM_DATA : inout slv32 -- sram: data lines
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);
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end component;
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end package s3boardlib;
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