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154 lines
5.1 KiB
VHDL
154 lines
5.1 KiB
VHDL
-- $Id: pdp11_gr.vhd 1310 2022-10-27 16:15:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_gr - syn
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-- Description: pdp11: general registers
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--
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-- Dependencies: memlib/ram_1swar_1ar_gen
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--
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
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-- Revision History:
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-- Date Rev Version Comment
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-- 2022-10-25 1309 1.0.3 rename _gpr -> _gr
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-- 2019-08-17 1203 1.0.2 fix for ghdl V0.36 -Whide warnings
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-- 2011-11-18 427 1.0.4 now numeric_std clean
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-- 2008-08-22 161 1.0.3 rename ubf_ -> ibf_; use iblib
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-- 2007-12-30 108 1.0.2 use ubf_byte[01]
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.iblib.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_gr is -- general registers
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port (
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CLK : in slbit; -- clock
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DIN : in slv16; -- input data
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ASRC : in slv3; -- source register number
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ADST : in slv3; -- destination register number
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MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
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RSET : in slbit; -- register set
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WE : in slbit; -- write enable
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BYTOP : in slbit; -- byte operation (write low byte only)
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PCINC : in slbit; -- increment PC
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DSRC : out slv16; -- source register data
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DDST : out slv16; -- destination register data
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PC : out slv16 -- current PC value
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);
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end pdp11_gr;
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architecture syn of pdp11_gr is
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-- --------------------------------------
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-- the register map determines the internal register file storage address
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-- of a register. The mapping is
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-- ADDR RNUM SET MODE
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-- 0000 000 0 -- R0 set 0
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-- 0001 001 0 -- R1 set 0
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-- 0010 010 0 -- R2 set 0
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-- 0011 011 0 -- R3 set 0
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-- 0100 100 0 -- R4 set 0
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-- 0101 101 0 -- R5 set 0
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-- 0110 110 - 00 SP kernel mode
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-- 0111 110 - 01 SP supervisor mode
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-- 1000 000 1 -- R0 set 1
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-- 1001 001 1 -- R1 set 1
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-- 1010 010 1 -- R2 set 1
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-- 1011 011 1 -- R3 set 1
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-- 1100 100 1 -- R4 set 1
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-- 1101 101 1 -- R5 set 1
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-- 1110 111 - -- PC
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-- 1111 110 - 11 SP user mode
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procedure do_regmap (
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signal PRNUM : in slv3; -- register number
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signal PMODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
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signal PRSET : in slbit; -- register set
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signal PADDR : out slv4 -- internal address in regfile
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) is
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begin
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if PRNUM = c_gr_pc then
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PADDR <= "1110";
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elsif PRNUM = c_gr_sp then
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PADDR <= PMODE(1) & "11" & PMODE(0);
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else
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PADDR <= PRSET & PRNUM;
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end if;
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end procedure do_regmap;
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-- --------------------------------------
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signal MASRC : slv4 := (others=>'0'); -- mapped source register address
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signal MADST : slv4 := (others=>'0'); -- mapped destination register address
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signal WE1 : slbit := '0'; -- write enable high byte
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signal MEMSRC : slv16 := (others=>'0');-- source reg data from memory
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signal MEMDST : slv16 := (others=>'0');-- destination reg data from memory
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signal R_PC : slv16 := (others=>'0'); -- PC register
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begin
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do_regmap(PRNUM => ASRC, PMODE => MODE, PRSET => RSET, PADDR => MASRC);
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do_regmap(PRNUM => ADST, PMODE => MODE, PRSET => RSET, PADDR => MADST);
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WE1 <= WE and not BYTOP;
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GR_LOW : ram_1swar_1ar_gen
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generic map (
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AWIDTH => 4,
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DWIDTH => 8)
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port map (
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CLK => CLK,
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WE => WE,
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ADDRA => MADST,
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ADDRB => MASRC,
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DI => DIN(ibf_byte0),
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DOA => MEMDST(ibf_byte0),
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DOB => MEMSRC(ibf_byte0));
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GR_HIGH : ram_1swar_1ar_gen
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generic map (
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AWIDTH => 4,
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DWIDTH => 8)
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port map (
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CLK => CLK,
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WE => WE1,
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ADDRA => MADST,
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ADDRB => MASRC,
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DI => DIN(ibf_byte1),
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DOA => MEMDST(ibf_byte1),
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DOB => MEMSRC(ibf_byte1));
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proc_pc : process (CLK)
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alias R_PC15 : slv15 is R_PC(15 downto 1); -- upper 15 bit of PC
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begin
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if rising_edge(CLK) then
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if WE='1' and ADST=c_gr_pc then
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R_PC(ibf_byte0) <= DIN(ibf_byte0);
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if BYTOP = '0' then
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R_PC(ibf_byte1) <= DIN(ibf_byte1);
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end if;
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elsif PCINC = '1' then
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R_PC15 <= slv(unsigned(R_PC15) + 1);
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end if;
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end if;
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end process proc_pc;
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DSRC <= R_PC when ASRC=c_gr_pc else MEMSRC;
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DDST <= R_PC when ADST=c_gr_pc else MEMDST;
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PC <= R_PC;
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end syn;
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