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3f455d5236
- re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std
119 lines
4.1 KiB
VHDL
119 lines
4.1 KiB
VHDL
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: sn_humanio - syn
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-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3
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--
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-- Dependencies: xlib/iob_reg_o_gen
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-- bpgen/bp_swibtnled
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-- bpgen/sn_4x7segctl
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--
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
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-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
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-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
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-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
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-- 2011-07-02 387 1.1.2 use bp_swibtnled
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-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
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-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
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-- 2010-04-10 275 1.0 Initial version
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------------------------------------------------------------------------------
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.bpgenlib.all;
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-- ----------------------------------------------------------------------------
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entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
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generic (
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BWIDTH : positive := 4; -- BTN port width
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DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_MSEC : in slbit; -- 1 ms clock enable
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SWI : out slv8; -- switch settings, debounced
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BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
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LED : in slv8; -- led data
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DSP_DAT : in slv16; -- display data
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DSP_DP : in slv4; -- display decimal points
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I_SWI : in slv8; -- pad-i: switches
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I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
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O_LED : out slv8; -- pad-o: leds
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O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
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O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
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);
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end sn_humanio;
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architecture syn of sn_humanio is
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signal N_ANO_N : slv4 := (others=>'0');
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signal N_SEG_N : slv8 := (others=>'0');
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begin
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IOB_ANO_N : iob_reg_o_gen
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generic map (DWIDTH => 4)
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port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
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IOB_SEG_N : iob_reg_o_gen
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generic map (DWIDTH => 8)
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port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
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HIO : bp_swibtnled
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generic map (
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SWIDTH => 8,
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BWIDTH => BWIDTH,
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LWIDTH => 8,
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DEBOUNCE => DEBOUNCE)
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port map (
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CLK => CLK,
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RESET => RESET,
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CE_MSEC => CE_MSEC,
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SWI => SWI,
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BTN => BTN,
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LED => LED,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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O_LED => O_LED
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);
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DRV : sn_4x7segctl
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generic map (
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CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
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port map (
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CLK => CLK,
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DIN => DSP_DAT,
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DP => DSP_DP,
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ANO_N => N_ANO_N,
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SEG_N => N_SEG_N
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);
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end syn;
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