mirror of
https://github.com/wfjm/w11.git
synced 2026-02-07 17:11:46 +00:00
cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
FLOWTYPE = FPGA_SYNTHESIS;
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#
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# $Id: syn_s6_speed.opt 456 2012-02-05 22:19:44Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2012-02-05 456 1.1 use $top_entity variable for -top attribute
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# 2011-08-13 405 1.0 Initial version
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#
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# Derived from ISE xst_mixed.opt
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#
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# ----------------------------------------------------------------------------
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# Options for XST
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#
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Program xst
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-ifn <design>_xst.scr; # input XST script file
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-ofn <design>_xst.log; # output XST log file
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-intstyle xflow; # Message Reporting Style
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#
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# ParamFile lists the XST Properties that can be set by the user.
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#
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ParamFile: <design>_xst.scr
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"run";
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#
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# Global Synthesis Options
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#
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"-ifn <synthdesign>"; # Input/Project File Name
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"-ifmt mixed"; # Input Format (Verilog and VHDL)
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"-ofn <design>"; # Output File Name
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"-ofmt ngc"; # Output File Format
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"-top $top_entity"; # Top Design Name
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"-p <partname>"; # Target Device
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"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
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"-opt_level 2"; # Optimization Effort Criteria: 2=High
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"-uc <design>.xcf"; # Constraint File name
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#
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# The following are HDL Options
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#
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End ParamFile
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End Program xst
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#
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