mirror of
https://github.com/wfjm/w11.git
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cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
148 lines
3.6 KiB
VHDL
148 lines
3.6 KiB
VHDL
-- $Id: byte2word.vhd 432 2011-11-25 20:16:28Z mueller $
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: byte2word - syn
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-- Description: 2 byte -> 1 word stream converter
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 12.1; ghdl 0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-21 432 1.0.1 now numeric_std clean
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-- 2011-07-30 400 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity byte2word is -- 2 byte -> 1 word stream converter
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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DI : in slv8; -- input data (byte)
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ENA : in slbit; -- write enable
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BUSY : out slbit; -- write port hold
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DO : out slv16; -- output data (word)
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VAL : out slbit; -- read valid
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HOLD : in slbit; -- read hold
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ODD : out slbit -- odd byte pending
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);
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end byte2word;
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architecture syn of byte2word is
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type state_type is (
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s_idle,
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s_vall,
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s_valw
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);
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type regs_type is record
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datl : slv8; -- lsb data
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dath : slv8; -- msb data
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state : state_type; -- state
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end record regs_type;
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constant regs_init : regs_type := (
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(others=>'0'),
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(others=>'0'),
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s_idle
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, DI, ENA, HOLD)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ival : slbit := '0';
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variable ibusy : slbit := '0';
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variable iodd : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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ival := '0';
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ibusy := '0';
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iodd := '0';
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case r.state is
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when s_idle =>
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if ENA = '1' then
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n.datl := DI;
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n.state := s_vall;
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end if;
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when s_vall =>
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iodd := '1';
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if ENA = '1' then
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n.dath := DI;
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n.state := s_valw;
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end if;
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when s_valw =>
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ival := '1';
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if HOLD = '0' then
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if ENA = '1' then
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n.datl := DI;
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n.state := s_vall;
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else
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n.state := s_idle;
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end if;
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else
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ibusy := '1';
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end if;
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when others => null;
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end case;
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N_REGS <= n;
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DO <= r.dath & r.datl;
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VAL <= ival;
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BUSY <= ibusy;
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ODD <= iodd;
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end process proc_next;
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end syn;
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