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3f455d5236
- re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std
84 lines
2.7 KiB
VHDL
84 lines
2.7 KiB
VHDL
-- $Id: crc8.vhd 410 2011-09-18 11:23:09Z mueller $
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: crc8 - syn
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-- Description: 8bit CRC generator, use 'A6' polynomial of Koopman and
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-- Chakravarty. Has HD=3 for up to 247 bits and optimal HD=2
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-- error detection for longer messages:
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--
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-- x^8 + x^6 + x^3 + x^2 + 1 (0xa6)
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--
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-- It is irreducible, and can be implemented with <= 37 xor's
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-- This polynomial is described in
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-- http://dx.doi.org/10.1109%2FDSN.2004.1311885
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.29
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-09-17 410 13.1 O40d xc3s1200e-4 8 25 - 13 (A6 polynom)
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-- 2011-09-17 409 13.1 O40d xc3s1200e-4 8 18 - 10 (SAE J1850)
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-09-17 409 1.1 use now 'A6' polynomial of Koopman et al.
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-- 2011-08-14 406 1.0.1 remove superfluous variable r
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.comlib.all;
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entity crc8 is -- crc-8 generator, checker
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generic (
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INIT: slv8 := "00000000"); -- initial state of crc register
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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ENA : in slbit; -- update enable
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DI : in slv8; -- input data
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CRC : out slv8 -- crc code
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);
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end crc8;
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architecture syn of crc8 is
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signal R_CRC : slv8 := INIT; -- state registers
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_CRC <= INIT;
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else
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if ENA = '1' then
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R_CRC <= crc8_update(R_CRC, DI);
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end if;
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end if;
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end if;
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end process proc_regs;
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CRC <= R_CRC;
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end syn;
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